From 09f892a945ccf909de4cde9d49094293ade852fe Mon Sep 17 00:00:00 2001
From: umarcor <unai.martinezcorral@ehu.eus>
Date: Tue, 13 Oct 2020 21:26:16 +0200
Subject: [PATCH] mixed-hdl: remove '-q' from yosys call'

Co-authored-by: T. Meissner <programming@goodcleanfun.de>
---
 mixed-hdl/blink/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mixed-hdl/blink/Makefile b/mixed-hdl/blink/Makefile
index 51a4a163..59ea6859 100644
--- a/mixed-hdl/blink/Makefile
+++ b/mixed-hdl/blink/Makefile
@@ -29,7 +29,7 @@ blink.json: $(VHDL_SYN_FILES) $(VERILOG_SYN_FILES)
 		"$(GHDLSYNTH) $(GHDL_FLAGS) $(VHDL_SYN_FILES) -e; \
 		synth_ice40 \
 		-top Fomu_Blink \
-		-json $@" -q $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
+		-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
 
 # Use **nextpnr** to generate the FPGA configuration.
 # This is called the **place** and **route** step.