fix unintended

initia-labs · Nov 14, 2024 · 4d66ca1 · 4d66ca1
1 parent 1a913c2
commit 4d66ca1
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diff --git a/.github/config/.codespellignore b/.github/config/.codespellignore
@@ -3,3 +3,4 @@ minitia
 expRes
 crate
 Hel
+ser
diff --git a/crates/types/src/serde_helper/vec_bytes.rs b/crates/types/src/serde_helper/vec_bytes.rs
@@ -3,7 +3,7 @@
 
 use serde::{
     de::Deserializer,
-    set::{SerializeSeq, Serializer},
+    ser::{SerializeSeq, Serializer},
     Deserialize,
 };
 

diff --git a/precompile/binaries/minlib/multisig.mv b/precompile/binaries/minlib/multisig.mv
diff --git a/precompile/binaries/stdlib/minitswap.mv b/precompile/binaries/stdlib/minitswap.mv
diff --git a/precompile/binaries/stdlib/multisig.mv b/precompile/binaries/stdlib/multisig.mv
-Original file line number
+Diff line change
@@ Expand Up / @@ -3,3 +3,4 @@ minitia @@
     expRes
     crate
     Hel
+    ser