diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-B6-0.json b/src/PMURegisterDeclarations/GenuineIntel-6-B6-0.json new file mode 100644 index 00000000..e3b4a8ed --- /dev/null +++ b/src/PMURegisterDeclarations/GenuineIntel-6-B6-0.json @@ -0,0 +1,145 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex8" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex16" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 8c8e0b2f..67b68e52 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -752,6 +752,7 @@ void PCM::initCStateSupportTables() case SPR: case EMR: case GNR: + case GRR: case SRF: PCM_CSTATE_ARRAY(pkgCStateMsr, PCM_PARAM_PROTECT({0, 0, 0x60D, 0, 0, 0, 0x3F9, 0, 0, 0, 0}) ); case HASWELL_ULT: @@ -809,6 +810,7 @@ void PCM::initCStateSupportTables() case SPR: case EMR: case GNR: + case GRR: case SRF: PCM_CSTATE_ARRAY(coreCStateMsr, PCM_PARAM_PROTECT({0, 0, 0, 0x3FC, 0, 0, 0x3FD, 0x3FE, 0, 0, 0}) ); case KNL: @@ -1666,6 +1668,7 @@ bool PCM::detectNominalFrequency() || cpu_family_model == EMR || cpu_family_model == GNR || cpu_family_model == SRF + || cpu_family_model == GRR ) ? (100000000ULL) : (133333333ULL); nominal_frequency = ((freq >> 8) & 255) * bus_freq; @@ -1963,6 +1966,7 @@ void PCM::initUncoreObjects() case SPR: case EMR: case GNR: + case GRR: case SRF: { bool failed = false; @@ -2170,6 +2174,28 @@ void PCM::initUncorePMUsDirect() ); } break; + case GRR: + uncorePMUs[s].resize(1); + { + std::vector > CounterControlRegs{ + std::make_shared(handle, GRR_UBOX_MSR_PMON_CTL0_ADDR), + std::make_shared(handle, GRR_UBOX_MSR_PMON_CTL1_ADDR) + }, + CounterValueRegs{ + std::make_shared(handle, GRR_UBOX_MSR_PMON_CTR0_ADDR), + std::make_shared(handle, GRR_UBOX_MSR_PMON_CTR1_ADDR) + }; + uncorePMUs[s][0][UBOX_PMU_ID].push_back( + std::make_shared( + std::make_shared(handle, GRR_UBOX_MSR_PMON_BOX_CTL_ADDR), + CounterControlRegs, + CounterValueRegs, + std::make_shared(handle, GRR_UCLK_FIXED_CTL_ADDR), + std::make_shared(handle, GRR_UCLK_FIXED_CTR_ADDR) + ) + ); + } + break; default: if (isServerCPU() && hasPCICFGUncore()) { @@ -2349,6 +2375,7 @@ void PCM::initUncorePMUsDirect() switch (cpu_family_model) { case GNR: + case GRR: case SRF: uncorePMUs[s].resize(1); if (safe_getenv("PCM_NO_PCIE_GEN5_DISCOVERY") == std::string("1")) @@ -2474,6 +2501,26 @@ void PCM::initUncorePMUsDirect() } } break; + case PCM::GRR: + for (uint32 s = 0; s < (uint32)num_sockets; ++s) + { + auto & handle = MSR[socketRefCore[s]]; + for (int unit = 0; unit < GRR_M2IOSF_NUM; ++unit) + { + iioPMUs[s][unit] = UncorePMU( + std::make_shared(handle, GRR_M2IOSF_IIO_UNIT_CTL + GRR_M2IOSF_REG_STEP * unit), + std::make_shared(handle, GRR_M2IOSF_IIO_CTL0 + GRR_M2IOSF_REG_STEP * unit + 0), + std::make_shared(handle, GRR_M2IOSF_IIO_CTL0 + GRR_M2IOSF_REG_STEP * unit + 1), + std::make_shared(handle, GRR_M2IOSF_IIO_CTL0 + GRR_M2IOSF_REG_STEP * unit + 2), + std::make_shared(handle, GRR_M2IOSF_IIO_CTL0 + GRR_M2IOSF_REG_STEP * unit + 3), + std::make_shared(handle, GRR_M2IOSF_IIO_CTR0 + GRR_M2IOSF_REG_STEP * unit + 0), + std::make_shared(handle, GRR_M2IOSF_IIO_CTR0 + GRR_M2IOSF_REG_STEP * unit + 1), + std::make_shared(handle, GRR_M2IOSF_IIO_CTR0 + GRR_M2IOSF_REG_STEP * unit + 2), + std::make_shared(handle, GRR_M2IOSF_IIO_CTR0 + GRR_M2IOSF_REG_STEP * unit + 3) + ); + } + } + break; } //init the IDX accelerator auto createIDXPMU = [](const size_t addr, const size_t mapSize, const size_t numaNode, const size_t socketId) -> IDX_PMU @@ -2670,6 +2717,12 @@ void PCM::initUncorePMUsDirect() IRP_CTR_REG_OFFSET = BHS_IRP_CTR_REG_OFFSET; IRP_UNIT_CTL = BHS_IRP_UNIT_CTL; break; + case GRR: + irpStacks = GRR_M2IOSF_NUM; + IRP_CTL_REG_OFFSET = GRR_IRP_CTL_REG_OFFSET; + IRP_CTR_REG_OFFSET = GRR_IRP_CTR_REG_OFFSET; + IRP_UNIT_CTL = GRR_IRP_UNIT_CTL; + break; } irpPMUs.resize(num_sockets); if (IRP_UNIT_CTL) @@ -3279,6 +3332,7 @@ bool PCM::isCPUModelSupported(const int model_) || model_ == SPR || model_ == EMR || model_ == GNR + || model_ == GRR || model_ == SRF ); } @@ -3573,6 +3627,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter L3CacheHitsAvailable = true; core_gen_counter_num_used = 4; break; + case GRR: case SRF: LLCArchEventInit(coreEventDesc); coreEventDesc[2].event_number = CMT_MEM_LOAD_RETIRED_L2_MISS_EVTNR; @@ -4918,6 +4973,8 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const return "Emerald Rapids-SP"; case GNR: return "Granite Rapids-SP"; + case GRR: + return "Grand Ridge"; case SRF: return "Sierra Forest"; } @@ -7656,6 +7713,11 @@ void ServerUncorePMUs::initRegisterLocations(const PCM * pcm) PCM_PCICFG_M2M_INIT(3, SERVER) } break; + case PCM::GRR: + { + // placeholder to init GRR PCICFG + } + break; default: std::cerr << "Error: Uncore PMU for processor with id 0x" << std::hex << cpu_family_model << std::dec << " is not supported.\n"; throw std::exception(); @@ -8029,6 +8091,9 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm) switch (cpu_family_model) { + case PCM::GRR: + initBHSiMCPMUs(2); + break; case PCM::GNR: case PCM::SRF: initBHSiMCPMUs(12); @@ -8818,6 +8883,7 @@ void ServerUncorePMUs::programServerUncoreMemoryMetrics(const ServerUncoreMemory } break; case PCM::GNR: + case PCM::GRR: case PCM::SRF: if (metrics == PmemMemoryMode) { @@ -8913,6 +8979,7 @@ void ServerUncorePMUs::program() EDCCntConfig[EventPosition::WRITE] = MCCntConfig[EventPosition::WRITE] = MC_CH_PCI_PMON_CTL_EVENT(0x05) + MC_CH_PCI_PMON_CTL_UMASK(0xf0); // monitor writes on counter 1: CAS_COUNT.WR break; case PCM::GNR: + case PCM::GRR: case PCM::SRF: MCCntConfig[EventPosition::READ] = MC_CH_PCI_PMON_CTL_EVENT(0x05) + MC_CH_PCI_PMON_CTL_UMASK(0xcf); // monitor reads on counter 0: CAS_COUNT_SCH0.RD MCCntConfig[EventPosition::WRITE] = MC_CH_PCI_PMON_CTL_EVENT(0x05) + MC_CH_PCI_PMON_CTL_UMASK(0xf0); // monitor writes on counter 1: CAS_COUNT_SCH0.WR @@ -9045,6 +9112,7 @@ uint64 ServerUncorePMUs::getImcReadsForChannels(uint32 beginChannel, uint32 endC switch (cpu_family_model) { case PCM::GNR: + case PCM::GRR: case PCM::SRF: result += getMCCounter(i, EventPosition::READ2); break; @@ -9062,6 +9130,7 @@ uint64 ServerUncorePMUs::getImcWrites() switch (cpu_family_model) { case PCM::GNR: + case PCM::GRR: case PCM::SRF: result += getMCCounter(i, EventPosition::WRITE2); break; @@ -9784,6 +9853,7 @@ uint64 PCM::CX_MSR_PMON_CTRY(uint32 Cbo, uint32 Ctr) const case SPR: case EMR: case GNR: + case GRR: case SRF: return SPR_CHA0_MSR_PMON_CTR0 + SPR_CHA_MSR_STEP * Cbo + Ctr; @@ -9815,6 +9885,7 @@ uint64 PCM::CX_MSR_PMON_BOX_FILTER(uint32 Cbo) const case SPR: case EMR: case GNR: + case GRR: case SRF: return SPR_CHA0_MSR_PMON_BOX_FILTER + SPR_CHA_MSR_STEP * Cbo; @@ -9859,6 +9930,7 @@ uint64 PCM::CX_MSR_PMON_CTLY(uint32 Cbo, uint32 Ctl) const case SPR: case EMR: case GNR: + case GRR: case SRF: return SPR_CHA0_MSR_PMON_CTL0 + SPR_CHA_MSR_STEP * Cbo + Ctl; @@ -9889,6 +9961,7 @@ uint64 PCM::CX_MSR_PMON_BOX_CTL(uint32 Cbo) const case SPR: case EMR: case GNR: + case GRR: case SRF: return SPR_CHA0_MSR_PMON_BOX_CTRL + SPR_CHA_MSR_STEP * Cbo; @@ -9964,6 +10037,7 @@ uint32 PCM::getMaxNumOfCBoxesInternal() const uint64 val = 0; switch (cpu_family_model) { + case GRR: case GNR: case SRF: { @@ -10079,6 +10153,9 @@ void PCM::programIIOCounters(uint64 rawEvents[4], int IIOStack) int stacks_count; switch (getCPUFamilyModel()) { + case PCM::GRR: + stacks_count = GRR_M2IOSF_NUM; + break; case PCM::GNR: case PCM::SRF: stacks_count = BHS_M2IOSF_NUM; @@ -10175,6 +10252,7 @@ void PCM::programPCIeEventGroup(eventGroup_t &eventGroup) switch (cpu_family_model) { case PCM::GNR: + case PCM::GRR: case PCM::SRF: case PCM::SPR: case PCM::EMR: @@ -10228,6 +10306,7 @@ void PCM::programCbo(const uint64 * events, const uint32 opCode, const uint32 nc && EMR != cpu_family_model && GNR != cpu_family_model && SRF != cpu_family_model + && GRR != cpu_family_model ) { programCboOpcodeFilter(opCode, pmu, nc_, 0, loc, rem); @@ -10728,6 +10807,7 @@ void UncorePMU::freeze(const uint32 extra) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GRR: case PCM::SRF: *unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ; break; @@ -10743,6 +10823,7 @@ void UncorePMU::unfreeze(const uint32 extra) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GRR: case PCM::SRF: *unitControl = 0; break; @@ -10763,6 +10844,7 @@ bool UncorePMU::initFreeze(const uint32 extra, const char* xPICheckMsg) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GRR: case PCM::SRF: *unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ; // freeze *unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ + SPR_UNC_PMON_UNIT_CTL_RST_CONTROL; // freeze and reset control registers @@ -10802,6 +10884,7 @@ void UncorePMU::resetUnfreeze(const uint32 extra) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GRR: case PCM::SRF: *unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ + SPR_UNC_PMON_UNIT_CTL_RST_COUNTERS; // freeze and reset counter registers *unitControl = 0; // unfreeze diff --git a/src/cpucounters.h b/src/cpucounters.h index 3969cf53..a5d39422 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1250,6 +1250,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GRR: case SRF: *ctrl = *curEvent; break; @@ -1902,6 +1903,7 @@ class PCM_API PCM GNR = PCM_CPU_FAMILY_MODEL(6, 173), SRF = PCM_CPU_FAMILY_MODEL(6, 175), GNR_D = PCM_CPU_FAMILY_MODEL(6, 174), + GRR = PCM_CPU_FAMILY_MODEL(6, 182), END_OF_MODEL_LIST = 0x0ffff }; @@ -2000,6 +2002,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GRR: case SRF: return (serverUncorePMUs.size() && serverUncorePMUs[0].get()) ? (serverUncorePMUs[0]->getNumQPIPorts()) : 0; } @@ -2027,6 +2030,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GRR: case SRF: case BDX: case KNL: @@ -2056,6 +2060,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GRR: case SRF: case BDX: case KNL: @@ -2088,6 +2093,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GRR: case SRF: case BDX: case KNL: @@ -2153,6 +2159,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GRR: case SRF: return 6; } @@ -2206,6 +2213,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GRR: case SRF: case KNL: return true; @@ -2473,6 +2481,7 @@ class PCM_API PCM || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR || cpu_family_model == PCM::SRF + || cpu_family_model == PCM::GRR ); } @@ -2491,6 +2500,7 @@ class PCM_API PCM || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR || cpu_family_model == PCM::SRF + || cpu_family_model == PCM::GRR ); } @@ -2597,6 +2607,7 @@ class PCM_API PCM || cpu_family_model == PCM::SNOWRIDGE || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR + || cpu_family_model == PCM::GRR || cpu_family_model == PCM::SRF || cpu_family_model == PCM::GNR ); @@ -2702,6 +2713,7 @@ class PCM_API PCM || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR || cpu_family_model == PCM::SRF + || cpu_family_model == PCM::GRR || cpu_family_model == PCM::BDX || cpu_family_model == PCM::KNL ); @@ -2748,6 +2760,7 @@ class PCM_API PCM || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR || cpu_family_model == PCM::SRF + || cpu_family_model == PCM::GRR ); } @@ -3434,6 +3447,7 @@ double getDRAMConsumedJoules(const CounterStateType & before, const CounterState || PCM::ICX == cpu_family_model || PCM::GNR == cpu_family_model || PCM::SRF == cpu_family_model + || PCM::GRR == cpu_family_model || PCM::KNL == cpu_family_model ) { /* as described in sections 5.3.2 (DRAM_POWER_INFO) and 5.3.3 (DRAM_ENERGY_STATUS) of @@ -4279,6 +4293,7 @@ uint64 getL2CacheMisses(const CounterStateType & before, const CounterStateType || cpu_family_model == PCM::ELKHART_LAKE || cpu_family_model == PCM::JASPER_LAKE || cpu_family_model == PCM::SRF + || cpu_family_model == PCM::GRR || cpu_family_model == PCM::ADL || cpu_family_model == PCM::RPL || cpu_family_model == PCM::MTL @@ -4390,6 +4405,7 @@ uint64 getL3CacheHitsSnoop(const CounterStateType & before, const CounterStateTy if (!pcm->isL3CacheHitsSnoopAvailable()) return 0; const auto cpu_family_model = pcm->getCPUFamilyModel(); if (cpu_family_model == PCM::SNOWRIDGE + || cpu_family_model == PCM::GRR || cpu_family_model == PCM::ELKHART_LAKE || cpu_family_model == PCM::JASPER_LAKE || cpu_family_model == PCM::SRF diff --git a/src/opCode-6-182.txt b/src/opCode-6-182.txt new file mode 100644 index 00000000..c3ccfbc9 --- /dev/null +++ b/src/opCode-6-182.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index 07a01311..8c77f038 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -38,6 +38,8 @@ using namespace pcm; #define NIS_DID 0x18D1 #define HQM_DID 0x270B +#define GRR_QAT_VRP_DID 0x5789 // Virtual Root Port to integrated QuickAssist (GRR QAT) +#define GRR_NIS_VRP_DID 0x5788 // VRP to Network Interface and Scheduler (GRR NIS) #define ROOT_BUSES_OFFSET 0xCC #define ROOT_BUSES_OFFSET_2 0xD0 @@ -238,6 +240,32 @@ static const std::string spr_mcc_iio_stack_names[] = { "IIO Stack 10 - DMI ", }; +// MS2IOSF stack IDs in CHA notation +#define GRR_PCH_DSA_GEN4_SAD_ID 0 +#define GRR_DLB_SAD_ID 1 +#define GRR_NIS_QAT_SAD_ID 2 + +#define GRR_PCH_DSA_GEN4_PMON_ID 2 +#define GRR_DLB_PMON_ID 1 +#define GRR_NIS_QAT_PMON_ID 0 + +// Stack 0 contains PCH, DSA and CPU PCIe Gen4 Complex +const std::map grr_sad_to_pmu_id_mapping = { + { GRR_PCH_DSA_GEN4_SAD_ID, GRR_PCH_DSA_GEN4_PMON_ID }, + { GRR_DLB_SAD_ID, GRR_DLB_PMON_ID }, + { GRR_NIS_QAT_SAD_ID, GRR_NIS_QAT_PMON_ID }, +}; + +#define GRR_DLB_PART_ID 0 +#define GRR_NIS_PART_ID 0 +#define GRR_QAT_PART_ID 1 + +static const std::string grr_iio_stack_names[3] = { + "IIO Stack 0 - NIS/QAT ", + "IIO Stack 1 - HQM ", + "IIO Stack 2 - PCH/DSA/PCIe " +}; + #define EMR_DMI_PMON_ID 7 #define EMR_PCIE_GEN5_0_PMON_ID 1 #define EMR_PCIE_GEN5_1_PMON_ID 2 @@ -1441,6 +1469,176 @@ bool EagleStreamPlatformMapping::pciTreeDiscover(std::vector& iios) override; +}; + +bool LoganvillePlatform::loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) +{ + struct iio_stack stack; + stack.busno = root_bus; + stack.iio_unit_id = stack_pmon_id; + stack.stack_name = grr_iio_stack_names[stack_pmon_id]; + + struct iio_bifurcated_part pch_part; + pch_part.part_id = 7; + struct pci* pci_dev = &pch_part.root_pci_dev; + pci_dev->bdf.busno = root_bus; + + if (probe_pci(pci_dev)) { + probeDeviceRange(pch_part.child_pci_devs, pci_dev->bdf.domainno, pci_dev->secondary_bus_number, pci_dev->subordinate_bus_number); + stack.parts.push_back(pch_part); + iio_on_socket.stacks.push_back(stack); + return true; + } + + return false; +} + +bool LoganvillePlatform::loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) +{ + struct iio_stack stack; + stack.busno = root_bus; + stack.iio_unit_id = stack_pmon_id; + stack.stack_name = grr_iio_stack_names[stack_pmon_id]; + + struct iio_bifurcated_part dlb_part; + dlb_part.part_id = GRR_DLB_PART_ID; + + for (uint8_t bus = root_bus; bus < 255; bus++) { + struct pci pci_dev(bus, 0x00, 0x00); + if (probe_pci(&pci_dev)) { + if ((pci_dev.vendor_id == PCM_INTEL_PCI_VENDOR_ID) && (pci_dev.device_id == HQMV25_DID)) { + dlb_part.root_pci_dev = pci_dev; + // Check Virtual RPs for DLB + for (uint8_t device = 0; device < 2; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev(bus, device, function); + if (probe_pci(&child_pci_dev)) { + dlb_part.child_pci_devs.push_back(child_pci_dev); + } + } + } + stack.parts.push_back(dlb_part); + iio_on_socket.stacks.push_back(stack); + return true; + } + } + } + + return false; +} + +bool LoganvillePlatform::loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) +{ + struct iio_stack stack; + stack.busno = root_bus; + stack.iio_unit_id = stack_pmon_id; + stack.stack_name = grr_iio_stack_names[stack_pmon_id]; + + // Probe NIS + { + struct iio_bifurcated_part nis_part; + nis_part.part_id = GRR_NIS_PART_ID; + struct pci pci_dev(root_bus, 0x04, 0x00); + if (probe_pci(&pci_dev)) { + nis_part.root_pci_dev = pci_dev; + for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 2; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev(bus, device, function); + if (probe_pci(&child_pci_dev)) { + nis_part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(nis_part); + } + } + + // Probe QAT + { + struct iio_bifurcated_part qat_part; + qat_part.part_id = GRR_QAT_PART_ID; + struct pci pci_dev(root_bus, 0x05, 0x00); + if (probe_pci(&pci_dev)) { + qat_part.root_pci_dev = pci_dev; + for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 17; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev(bus, device, function); + if (probe_pci(&child_pci_dev)) { + qat_part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(qat_part); + } + } + + iio_on_socket.stacks.push_back(stack); + return true; +} + +bool LoganvillePlatform::pciTreeDiscover(std::vector& iios) +{ + std::map sad_id_bus_map; + if (!getSadIdRootBusMap(0, sad_id_bus_map)) { + return false; + } + + if (sad_id_bus_map.size() != grr_sad_to_pmu_id_mapping.size()) { + cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << grr_sad_to_pmu_id_mapping.size() << endl; + return false; + } + + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = 0; + + for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) { + if (grr_sad_to_pmu_id_mapping.find(sad_id_bus_pair->first) == grr_sad_to_pmu_id_mapping.end()) { + cerr << "Cannot map SAD ID to PMON ID. Unknown ID: " << sad_id_bus_pair->first << endl; + return false; + } + int stack_pmon_id = grr_sad_to_pmu_id_mapping.at(sad_id_bus_pair->first); + int root_bus = sad_id_bus_pair->second; + switch (stack_pmon_id) { + case GRR_PCH_DSA_GEN4_PMON_ID: + if (!loganvillePchDsaPciStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { + return false; + } + break; + case GRR_DLB_PMON_ID: + if (!loganvilleDlbStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { + return false; + } + break; + case GRR_NIS_QAT_PMON_ID: + if (!loganvilleNacStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { + return false; + } + break; + default: + return false; + } + } + + std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); + + iios.push_back(iio_on_socket); + + return true; +} + void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int domain, int secondary, int subordinate) { for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) { @@ -1699,6 +1897,8 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f case PCM::SPR: case PCM::EMR: return std::unique_ptr{new EagleStreamPlatformMapping(cpu_family_model, sockets_count)}; + case PCM::GRR: + return std::unique_ptr{new LoganvillePlatform(cpu_family_model, sockets_count)}; case PCM::SRF: case PCM::GNR: return std::unique_ptr{new BirchStreamPlatform(cpu_family_model, sockets_count)}; @@ -1717,6 +1917,7 @@ ccr* get_ccr(PCM* m, uint64_t& ccr) case PCM::SNOWRIDGE: case PCM::SPR: case PCM::EMR: + case PCM::GRR: case PCM::SRF: case PCM::GNR: return new icx_ccr(ccr); diff --git a/src/pcm-memory.cpp b/src/pcm-memory.cpp index 5cd5d2a7..57d373d0 100644 --- a/src/pcm-memory.cpp +++ b/src/pcm-memory.cpp @@ -426,6 +426,7 @@ void printSocketBWFooter(PCM *m, uint32 no_columns, uint32 skt, const memdata_t if ( md->metrics == PartialWrites && m->getCPUFamilyModel() != PCM::SRF && m->getCPUFamilyModel() != PCM::GNR + && m->getCPUFamilyModel() != PCM::GRR ) { for (uint32 i=skt; i<(skt+no_columns); ++i) { @@ -735,6 +736,7 @@ void display_bandwidth_csv(PCM *m, memdata_t *md, uint64 /*elapsedTime*/, const if ( md->metrics == PartialWrites && m->getCPUFamilyModel() != PCM::GNR && m->getCPUFamilyModel() != PCM::SRF + && m->getCPUFamilyModel() != PCM::GRR ) { choose(outputType, @@ -994,6 +996,7 @@ void calculate_bandwidth(PCM *m, switch (cpu_family_model) { case PCM::GNR: + case PCM::GRR: case PCM::SRF: reads += getMCCounter(channel, ServerUncorePMUs::EventPosition::READ2, uncState1[skt], uncState2[skt]); writes += getMCCounter(channel, ServerUncorePMUs::EventPosition::WRITE2, uncState1[skt], uncState2[skt]); @@ -1059,6 +1062,7 @@ void calculate_bandwidth(PCM *m, else if ( cpu_family_model != PCM::GNR && cpu_family_model != PCM::SRF + && cpu_family_model != PCM::GRR ) { md.partial_write[skt] += (uint64)(getMCCounter(channel, ServerUncorePMUs::EventPosition::PARTIAL, uncState1[skt], uncState2[skt]) / (elapsedTime / 1000.0)); diff --git a/src/pcm-pcie.cpp b/src/pcm-pcie.cpp index 69d1c380..d361d225 100644 --- a/src/pcm-pcie.cpp +++ b/src/pcm-pcie.cpp @@ -99,6 +99,8 @@ IPlatform *IPlatform::getPlatform(PCM *m, bool csv, bool print_bandwidth, bool p case PCM::GNR: case PCM::SRF: return new BirchStreamPlatform(m, csv, print_bandwidth, print_additional_info, delay); + case PCM::GRR: + return new LoganvillePlatform(m, csv, print_bandwidth, print_additional_info, delay); case PCM::SPR: case PCM::EMR: return new EagleStreamPlatform(m, csv, print_bandwidth, print_additional_info, delay); diff --git a/src/pcm-pcie.h b/src/pcm-pcie.h index 0021047c..6b27c299 100644 --- a/src/pcm-pcie.h +++ b/src/pcm-pcie.h @@ -474,6 +474,136 @@ uint64 BirchStreamPlatform::getWriteBw() return (writeBw * 64ULL); } +// GRR + +class LoganvillePlatform: public LegacyPlatform +{ +public: + LoganvillePlatform(PCM *m, bool csv, bool bandwidth, bool verbose, uint32 delay) : + LegacyPlatform( {"PCIRdCur", "ItoM", "ItoMCacheNear", "UCRdF", "WiL", "WCiL", "WCiLF"}, + { + {0xC8F3FE00000435, 0xC8F3FD00000435, 0xCC43FE00000435, 0xCC43FD00000435}, + {0xCD43FE00000435, 0xCD43FD00000435, 0xC877DE00000135, 0xC87FDE00000135}, + {0xC86FFE00000135, 0xC867FE00000135,}, + }, + m, csv, bandwidth, verbose, delay) + { + }; + +private: + enum eventIdx { + PCIRdCur, + ItoM, + ItoMCacheNear, + UCRdF, + WiL, + WCiL, + WCiLF + }; + + enum Events { + PCIRdCur_miss, + PCIRdCur_hit, + ItoM_miss, + ItoM_hit, + ItoMCacheNear_miss, + ItoMCacheNear_hit, + UCRdF_miss, + WiL_miss, + WCiL_miss, + WCiLF_miss, + eventLast + }; + + virtual uint64 getReadBw(uint socket, eventFilter filter); + virtual uint64 getWriteBw(uint socket, eventFilter filter); + virtual uint64 getReadBw(); + virtual uint64 getWriteBw(); + virtual uint64 event(uint socket, eventFilter filter, uint idx); +}; + +uint64 LoganvillePlatform::event(uint socket, eventFilter filter, uint idx) +{ + uint64 event = 0; + switch (idx) + { + case PCIRdCur: + if (filter == TOTAL) + event = eventSample[socket][PCIRdCur_miss] + + eventSample[socket][PCIRdCur_hit]; + else if (filter == MISS) + event = eventSample[socket][PCIRdCur_miss]; + else if (filter == HIT) + event = eventSample[socket][PCIRdCur_hit]; + break; + case ItoM: + if (filter == TOTAL) + event = eventSample[socket][ItoM_miss] + + eventSample[socket][ItoM_hit]; + else if (filter == MISS) + event = eventSample[socket][ItoM_miss]; + else if (filter == HIT) + event = eventSample[socket][ItoM_hit]; + break; + case ItoMCacheNear: + if (filter == TOTAL) + event = eventSample[socket][ItoMCacheNear_miss] + + eventSample[socket][ItoMCacheNear_hit]; + else if (filter == MISS) + event = eventSample[socket][ItoMCacheNear_miss]; + else if (filter == HIT) + event = eventSample[socket][ItoMCacheNear_hit]; + break; + case UCRdF: + if (filter == TOTAL || filter == MISS) + event = eventSample[socket][UCRdF_miss]; + break; + case WiL: + if (filter == TOTAL || filter == MISS) + event = eventSample[socket][WiL_miss]; + break; + case WCiL: + if (filter == TOTAL || filter == MISS) + event = eventSample[socket][WCiL_miss]; + break; + case WCiLF: + if (filter == TOTAL || filter == MISS) + event = eventSample[socket][WCiLF_miss]; + break; + default: + break; + } + return event; +} + +uint64 LoganvillePlatform::getReadBw(uint socket, eventFilter filter) +{ + uint64 readBw = event(socket, filter, PCIRdCur); + return (readBw * 64ULL); +} + +uint64 LoganvillePlatform::getWriteBw(uint socket, eventFilter filter) +{ + uint64 writeBw = event(socket, filter, ItoM) + + event(socket, filter, ItoMCacheNear); + return (writeBw * 64ULL); +} +uint64 LoganvillePlatform::getReadBw() +{ + uint64 readBw = 0; + for (uint socket = 0; socket < m_socketCount; socket++) + readBw += (event(socket, TOTAL, PCIRdCur)); + return (readBw * 64ULL); +} + +uint64 LoganvillePlatform::getWriteBw() +{ + uint64 writeBw = 0; + for (uint socket = 0; socket < m_socketCount; socket++) + writeBw += (event(socket, TOTAL, ItoM) + + event(socket, TOTAL, ItoMCacheNear)); + return (writeBw * 64ULL); +} //SPR class EagleStreamPlatform: public LegacyPlatform diff --git a/src/types.h b/src/types.h index 09b24a06..f6f33ce2 100644 --- a/src/types.h +++ b/src/types.h @@ -1017,7 +1017,19 @@ constexpr auto BHS_UBOX_MSR_PMON_CTL1_ADDR = 0x3FF3; constexpr auto BHS_UBOX_MSR_PMON_CTR0_ADDR = 0x3FF8; constexpr auto BHS_UBOX_MSR_PMON_CTR1_ADDR = 0x3FF9; - +constexpr auto GRR_UCLK_FIXED_CTR_ADDR = 0x3F5F; +constexpr auto GRR_UCLK_FIXED_CTL_ADDR = 0x3F5E; +constexpr auto GRR_UBOX_MSR_PMON_BOX_CTL_ADDR = 0x3F50; +constexpr auto GRR_UBOX_MSR_PMON_CTL0_ADDR = 0x3F52; +constexpr auto GRR_UBOX_MSR_PMON_CTL1_ADDR = 0x3F53; +constexpr auto GRR_UBOX_MSR_PMON_CTR0_ADDR = 0x3F58; +constexpr auto GRR_UBOX_MSR_PMON_CTR1_ADDR = 0x3F59; + +constexpr auto GRR_M2IOSF_IIO_UNIT_CTL = 0x2900; +constexpr auto GRR_M2IOSF_IIO_CTR0 = 0x2908; +constexpr auto GRR_M2IOSF_IIO_CTL0 = 0x2902; +constexpr auto GRR_M2IOSF_REG_STEP = 0x10; +constexpr auto GRR_M2IOSF_NUM = 3; constexpr auto JKTIVT_UCLK_FIXED_CTR_ADDR = (0x0C09); constexpr auto JKTIVT_UCLK_FIXED_CTL_ADDR = (0x0C08); @@ -1247,6 +1259,14 @@ static const uint32 ICX_IIO_UNIT_CTL[] = { 0x0A50, 0x0A70, 0x0A90, 0x0AE0, 0x0B00, 0x0B20 }; +static const uint32 GRR_IRP_UNIT_CTL[] = { + 0x2A00, + 0x2A10, + 0x2A20 +}; + +#define GRR_IRP_CTL_REG_OFFSET (0x0002) +#define GRR_IRP_CTR_REG_OFFSET (0x0008) static const uint32 BHS_IRP_UNIT_CTL[] = { 0x2A00,