diff --git a/rmm/.cargo/config.toml b/rmm/.cargo/config.toml
index 9b9571e8d1e0..e77d4cd36576 100644
--- a/rmm/.cargo/config.toml
+++ b/rmm/.cargo/config.toml
@@ -2,5 +2,6 @@
 target = "aarch64-unknown-none-softfloat"
 rustflags = [
   "-C", "target-feature=+ecv",
+  "-C", "target-feature=+sme",
   "-C", "target-feature=+tlb-rmi"
 ]
diff --git a/rmm/src/exception/trap.rs b/rmm/src/exception/trap.rs
index 6f64d221cdae..db9d47427066 100644
--- a/rmm/src/exception/trap.rs
+++ b/rmm/src/exception/trap.rs
@@ -236,6 +236,7 @@ pub extern "C" fn handle_lower_exception(
                 rec.context.simd.is_used = true;
                 unsafe {
                     if rec.context.simd.is_saved {
+                        #[cfg(not(any(miri, test)))]
                         match Syndrome::from(esr) {
                             Syndrome::FPU => simd::restore_fpu(&rec.context.simd.fpu),
                             Syndrome::SVE | Syndrome::SME => {
diff --git a/rmm/src/realm/context.rs b/rmm/src/realm/context.rs
index 6d6cf4dc6960..040fa9a30445 100644
--- a/rmm/src/realm/context.rs
+++ b/rmm/src/realm/context.rs
@@ -84,6 +84,7 @@ impl Context {
         TPIDR_EL2.set(rec as *const _ as u64);
         gic::restore_state(rec);
         timer::restore_state(rec);
+        #[cfg(not(any(test, miri)))]
         simd::restore_state(rec);
     }
 
@@ -96,6 +97,7 @@ impl Context {
     pub unsafe fn from_current(rec: &mut Rec<'_>) {
         gic::save_state(rec);
         timer::save_state(rec);
+        #[cfg(not(any(test, miri)))]
         simd::save_state(rec);
     }
 }
diff --git a/rmm/src/simd.rs b/rmm/src/simd.rs
index e4fb84f994dc..37946d900445 100644
--- a/rmm/src/simd.rs
+++ b/rmm/src/simd.rs
@@ -84,6 +84,7 @@ lazy_static! {
         let mut sme_en: bool = false;
 
         trace!("Reading simd features");
+        #[cfg(not(any(test, miri)))]
         if ID_AA64PFR0_EL1.is_set(ID_AA64PFR0_EL1::SVE) {
             trace!("SVE is set");
             // Get effective vl
@@ -101,6 +102,7 @@ lazy_static! {
         }
 
         // init sme
+        #[cfg(not(any(test, miri)))]
         if ID_AA64PFR1_SME_EL1.is_set(ID_AA64PFR1_SME_EL1::SME) {
             trace!("SME is set");
             // Find the architecturally permitted SVL
@@ -258,6 +260,7 @@ pub fn save_state(rec: &mut Rec<'_>) {
         rec_simd.sve.zcr_el2 = ZCR_EL2.get();
         rec_simd.sve.zcr_el12 = ZCR_EL1.get();
         ZCR_EL2.set(ns_simd.sve.zcr_el2);
+        unimplemented!();
     } else {
         unsafe {
             if rec_simd.is_used {