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CI workflow for SystemVerilog syntax checking
main #60: Pull request #46 synchronize by Muxianesty
August 13, 2024 13:04 1m 31s check_verilog_ci
August 13, 2024 13:04 1m 31s
CI workflow for SystemVerilog syntax checking
main #59: Pull request #46 synchronize by Muxianesty
August 13, 2024 12:55 1m 24s check_verilog_ci
August 13, 2024 12:55 1m 24s
CI workflow for SystemVerilog syntax checking
main #58: Pull request #46 synchronize by Muxianesty
August 13, 2024 12:54 1m 35s check_verilog_ci
August 13, 2024 12:54 1m 35s
CI workflow for SystemVerilog syntax checking
main #57: Pull request #46 synchronize by Muxianesty
August 13, 2024 12:52 1m 30s check_verilog_ci
August 13, 2024 12:52 1m 30s
CI workflow for SystemVerilog syntax checking
main #56: Pull request #46 synchronize by Muxianesty
August 8, 2024 16:44 1m 28s check_verilog_ci
August 8, 2024 16:44 1m 28s
Merge pull request #45 from ispras/gen_stubs
main #50: Commit 768cca0 pushed by ssmolov
August 8, 2024 15:26 1m 46s master
August 8, 2024 15:26 1m 46s
SystemVerilog stubs generation
main #49: Pull request #45 synchronize by Muxianesty
August 8, 2024 15:23 1m 31s gen_stubs
August 8, 2024 15:23 1m 31s
SystemVerilog stubs generation
main #48: Pull request #45 synchronize by Muxianesty
August 8, 2024 15:19 1m 35s gen_stubs
August 8, 2024 15:19 1m 35s
SystemVerilog stubs generation
main #47: Pull request #45 synchronize by Muxianesty
August 8, 2024 15:12 1m 28s gen_stubs
August 8, 2024 15:12 1m 28s
SystemVerilog stubs generation
main #46: Pull request #45 synchronize by Muxianesty
August 8, 2024 14:56 1m 54s gen_stubs
August 8, 2024 14:56 1m 54s
SystemVerilog stubs generation
main #45: Pull request #45 synchronize by Muxianesty
August 8, 2024 13:33 1m 31s gen_stubs
August 8, 2024 13:33 1m 31s
SystemVerilog stubs generation
main #44: Pull request #45 synchronize by Muxianesty
August 8, 2024 11:35 1m 37s gen_stubs
August 8, 2024 11:35 1m 37s
SystemVerilog stubs generation
main #43: Pull request #45 synchronize by Muxianesty
August 8, 2024 11:26 45s gen_stubs
August 8, 2024 11:26 45s
SystemVerilog stubs generation
main #42: Pull request #45 opened by Muxianesty
August 8, 2024 11:23 40s gen_stubs
August 8, 2024 11:23 40s
Merge pull request #44 from ispras/fix_warnings
main #41: Commit 1b884c2 pushed by ssmolov
August 7, 2024 11:43 1m 40s master
August 7, 2024 11:43 1m 40s
Reduce the amount of compilation warnings
main #40: Pull request #44 opened by Muxianesty
August 5, 2024 16:17 1m 25s fix_warnings
August 5, 2024 16:17 1m 25s
Merge pull request #43 from ispras/output_formats_tests
main #39: Commit e0dc02f pushed by ssmolov
August 5, 2024 13:54 1m 29s master
August 5, 2024 13:54 1m 29s
Output format tests for SystemVerilog and DFCIR
main #38: Pull request #43 opened by Muxianesty
August 5, 2024 13:20 1m 31s output_formats_tests
August 5, 2024 13:20 1m 31s
Merge pull request #40 from ispras/firrtl_output_format
main #37: Commit 0773c98 pushed by ssmolov
August 5, 2024 13:06 1m 33s master
August 5, 2024 13:06 1m 33s
Merge pull request #41 from ispras/main-workflow-update-1
main #33: Commit 517edfd pushed by ssmolov
August 5, 2024 11:51 1m 19s master
August 5, 2024 11:51 1m 19s
Main CI workflow: Clang configuration
main #32: Pull request #41 opened by Muxianesty
August 2, 2024 19:44 1m 22s main-workflow-update-1
August 2, 2024 19:44 1m 22s