From 89a263af94a55525960c6ba9d04ffb9b577bb5f6 Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Fri, 2 Aug 2024 19:46:32 +0300 Subject: [PATCH 1/5] Scheduled FIRRTL output format implementation; minor refactoring, config and codestyle fixes. --- README.md | 1 + config.json | 4 ++- src/model/dfcir/CMakeLists.txt | 2 +- src/model/dfcxx/include/dfcxx/typedefs.h | 1 + .../dfcxx/includeDev/dfcxx/CMakeLists.txt | 2 +- src/model/dfcxx/lib/dfcxx/CMakeLists.txt | 12 +++++++ .../dfcxx/lib/dfcxx/IRbuilders/builder.cpp | 3 +- src/model/dfcxx/lib/dfcxx/converter.cpp | 31 +++++++++++++++++++ src/options.h | 6 ++++ 9 files changed, 58 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 756c0b9..11fafe5 100644 --- a/README.md +++ b/README.md @@ -218,6 +218,7 @@ The list of arguments for `hls`-mode is presented below: * `--config `: *required* filesystem-path option; used to specify the file for a JSON latency configuration file. Its format is presented in *JSON Configuration* section. * `--out-sv `: *optional* filesystem-path option; used to specify the output SystemVerilog file. * `--out-dfcir `: *optional* filesystem-path option; used to specify the output DFCIR file. +* `--out-firrtl `: *optional* filesystem-path option; used to specify the output FIRRTL file. * `-a` or `-l`: *required* flag; used to specify the chosen scheduling strategy - either as-soon-as-possible or linear programming. **Exactly one of these flags has to be specified**. **At least one of the `out-*` options has to be specified.** diff --git a/config.json b/config.json index ea64bdc..c66e696 100644 --- a/config.json +++ b/config.json @@ -3,6 +3,8 @@ "config" : "", "asap_scheduler" : false, "lp_scheduler" : false, - "sv_out" : "" + "out_sv" : "", + "out_dfcir" : "", + "out_firrtl" : "" } } diff --git a/src/model/dfcir/CMakeLists.txt b/src/model/dfcir/CMakeLists.txt index 19fe572..612caf4 100644 --- a/src/model/dfcir/CMakeLists.txt +++ b/src/model/dfcir/CMakeLists.txt @@ -3,6 +3,6 @@ project(DFCIR LANGUAGES CXX) set(CMAKE_CXX_STANDARD 17) # TODO: Figure out how to pass Tablegen includes the other way. # Issue #15 (https://github.com/ispras/utopia-hls/issues/15). -include_directories(${MLIR_INCLUDE_DIRS}) +include_directories(${MLIR_INCLUDE_DIRS}) add_subdirectory(include) add_subdirectory(lib) diff --git a/src/model/dfcxx/include/dfcxx/typedefs.h b/src/model/dfcxx/include/dfcxx/typedefs.h index 37a25f6..c313349 100644 --- a/src/model/dfcxx/include/dfcxx/typedefs.h +++ b/src/model/dfcxx/include/dfcxx/typedefs.h @@ -63,6 +63,7 @@ enum Scheduler { enum class OutputFormatID : uint8_t { SystemVerilog = 0, DFCIR, + FIRRTL, // Utility value. Constains the number of elements in the enum. COUNT }; diff --git a/src/model/dfcxx/includeDev/dfcxx/CMakeLists.txt b/src/model/dfcxx/includeDev/dfcxx/CMakeLists.txt index 11a4491..acc5058 100644 --- a/src/model/dfcxx/includeDev/dfcxx/CMakeLists.txt +++ b/src/model/dfcxx/includeDev/dfcxx/CMakeLists.txt @@ -1 +1 @@ -add_subdirectory(IRbuilders) \ No newline at end of file +add_subdirectory(IRbuilders) diff --git a/src/model/dfcxx/lib/dfcxx/CMakeLists.txt b/src/model/dfcxx/lib/dfcxx/CMakeLists.txt index dcf35fd..b01cb10 100644 --- a/src/model/dfcxx/lib/dfcxx/CMakeLists.txt +++ b/src/model/dfcxx/lib/dfcxx/CMakeLists.txt @@ -4,6 +4,17 @@ add_subdirectory(typebuilders) add_subdirectory(vars) add_subdirectory(varbuilders) +## By default LLVM, MLIR and DFCIR are compiled without RTTI, but not DFCxx. +## So using core Pass functionality from MLIR in converter.cpp causes +## linker-level errors ("undefined reference to `typeinfo for mlir::Pass'"). +## The following lines explicitly disable RTTI for DFCxx. +if (${CMAKE_CXX_COMPILER_ID} STREQUAL "MSVC") + set(DISABLE_RTTI_FLAG "/GR-") +else() + set(DISABLE_RTTI_FLAG "-fno-rtti") +endif() +add_definitions(${DISABLE_RTTI_FLAG}) + set(SOURCES kernel.cpp ${IR_BUILDERS_SOURCES} @@ -36,6 +47,7 @@ target_include_directories(DFCXX ## MLIRDFCIR is ensured to be compiled beforehand. target_link_libraries(DFCXX + PRIVATE $ PRIVATE $ PRIVATE $ PRIVATE $ diff --git a/src/model/dfcxx/lib/dfcxx/IRbuilders/builder.cpp b/src/model/dfcxx/lib/dfcxx/IRbuilders/builder.cpp index 5c60611..24a6773 100644 --- a/src/model/dfcxx/lib/dfcxx/IRbuilders/builder.cpp +++ b/src/model/dfcxx/lib/dfcxx/IRbuilders/builder.cpp @@ -6,9 +6,10 @@ // //===----------------------------------------------------------------------===// +#include "dfcxx/IRbuilders/builder.h" + #include "circt/Dialect/FIRRTL/FIRRTLDialect.h" #include "circt/Dialect/SV/SVDialect.h" -#include "dfcxx/IRbuilders/builder.h" #include "mlir/Parser/Parser.h" namespace dfcxx { diff --git a/src/model/dfcxx/lib/dfcxx/converter.cpp b/src/model/dfcxx/lib/dfcxx/converter.cpp index 483d94d..2ca79ca 100644 --- a/src/model/dfcxx/lib/dfcxx/converter.cpp +++ b/src/model/dfcxx/lib/dfcxx/converter.cpp @@ -9,10 +9,36 @@ #include "dfcxx/converter.h" #include "circt/Conversion/Passes.h" +#include "mlir/Pass/Pass.h" #include "mlir/Pass/PassManager.h" +#include + namespace dfcxx { +class DFCIRDumperPass: public PassWrapper> { +private: + llvm::raw_fd_ostream *stream; + +public: + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(DFCIRDumperPass) + + DFCIRDumperPass() = default; + + DFCIRDumperPass(llvm::raw_fd_ostream *stream) : DFCIRDumperPass() { + this->stream = stream; + } + + void runOnOperation() override { + return getOperation()->print(*stream); + } + +}; + +std::unique_ptr createDFCIRDumperPass(llvm::raw_fd_ostream *stream) { + return std::make_unique(stream); +} + DFCIRConverter::DFCIRConverter(const DFLatencyConfig &config) { this->config = LatencyConfig(); for (auto [op, latency]: config) { @@ -42,6 +68,11 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module, break; } + // Dump FIRRTL if the corresponding option is specified. + if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(FIRRTL)]) { + pm.addPass(createDFCIRDumperPass(stream)); + } + // Add FIRRTL->SystemVerilog passes if SystemVerilog output option is specified. if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(SystemVerilog)]) { pm.addPass(circt::createLowerFIRRTLToHWPass()); diff --git a/src/options.h b/src/options.h index 27d4f75..fc7c172 100644 --- a/src/options.h +++ b/src/options.h @@ -37,6 +37,7 @@ #define LP_SCHEDULER_JSON "lp_scheduler" #define OUT_SV_JSON "out_sv" #define OUT_DFCIR_JSON "out_dfcir" +#define OUT_FIRRTL_JSON "out_firrtl" //===----------------------------------------------------------------------===// // CLI args/flags definitions @@ -49,6 +50,7 @@ #define OUTPUT_GROUP "output" #define OUT_SV_ARG CLI_ARG("out-sv") #define OUT_DFCIR_ARG CLI_ARG("out-dfcir") +#define OUT_FIRRTL_ARG CLI_ARG("out-firrtl") //===----------------------------------------------------------------------===// @@ -185,6 +187,9 @@ struct HlsOptions final : public AppOptions { outputGroup->add_option(OUT_DFCIR_ARG, outNames[OUT_FORMAT_ID_INT(DFCIR)], "Path to output unscheduled DFCIR"); + outputGroup->add_option(OUT_FIRRTL_ARG, + outNames[OUT_FORMAT_ID_INT(FIRRTL)], + "Path to output scheduled FIRRTL"); outputGroup->require_option(); } @@ -194,6 +199,7 @@ struct HlsOptions final : public AppOptions { get(json, LP_SCHEDULER_JSON, lpScheduler); get(json, OUT_SV_JSON, outNames[OUT_FORMAT_ID_INT(SystemVerilog)]); get(json, OUT_DFCIR_JSON, outNames[OUT_FORMAT_ID_INT(DFCIR)]); + get(json, OUT_FIRRTL_JSON, outNames[OUT_FORMAT_ID_INT(FIRRTL)]); } std::string latConfigFile; From 310d3128354819dc2f06d7cc1ca77179c72bb241 Mon Sep 17 00:00:00 2001 From: Muxianesty <71048120+Muxianesty@users.noreply.github.com> Date: Fri, 2 Aug 2024 19:59:03 +0300 Subject: [PATCH 2/5] Namespace usage updated in `converter.cpp`. --- src/model/dfcxx/lib/dfcxx/converter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/model/dfcxx/lib/dfcxx/converter.cpp b/src/model/dfcxx/lib/dfcxx/converter.cpp index 2ca79ca..c43d8d6 100644 --- a/src/model/dfcxx/lib/dfcxx/converter.cpp +++ b/src/model/dfcxx/lib/dfcxx/converter.cpp @@ -16,7 +16,7 @@ namespace dfcxx { -class DFCIRDumperPass: public PassWrapper> { +class DFCIRDumperPass: public mlir::PassWrapper> { private: llvm::raw_fd_ostream *stream; From 8a793dd74c4ef980b0a2a342fd108ba2d51a6bc4 Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Mon, 5 Aug 2024 15:47:17 +0300 Subject: [PATCH 3/5] First output formats' test was added; minor codestyle fixes. --- test/model/dfcxx/CMakeLists.txt | 1 + test/model/dfcxx/addconst.cpp | 6 +++--- test/model/dfcxx/idct.cpp | 12 ++++++------ test/model/dfcxx/matrixmul2.cpp | 10 +++++----- test/model/dfcxx/movingsum.cpp | 10 +++++----- test/model/dfcxx/muxmul.cpp | 8 ++++---- test/model/dfcxx/output_formats.cpp | 24 ++++++++++++++++++++++++ test/model/dfcxx/polynomial2.cpp | 16 ++++++++-------- test/model/dfcxx/scalar3.cpp | 8 ++++---- 9 files changed, 60 insertions(+), 35 deletions(-) create mode 100644 test/model/dfcxx/output_formats.cpp diff --git a/test/model/dfcxx/CMakeLists.txt b/test/model/dfcxx/CMakeLists.txt index 290e8d2..8a6292a 100644 --- a/test/model/dfcxx/CMakeLists.txt +++ b/test/model/dfcxx/CMakeLists.txt @@ -6,5 +6,6 @@ set(DFCXX_TESTS model/dfcxx/addconst.cpp model/dfcxx/movingsum.cpp model/dfcxx/idct.cpp + model/dfcxx/output_formats.cpp PARENT_SCOPE ) diff --git a/test/model/dfcxx/addconst.cpp b/test/model/dfcxx/addconst.cpp index 28fe1c5..2996619 100644 --- a/test/model/dfcxx/addconst.cpp +++ b/test/model/dfcxx/addconst.cpp @@ -16,7 +16,7 @@ static const DFOutputPaths nullDevicePath = TEST(DFCxx, AddConstAddInt2Asap) { AddConst kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2} + {dfcxx::ADD_INT, 2} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -24,7 +24,7 @@ TEST(DFCxx, AddConstAddInt2Asap) { TEST(DFCxx, AddConstAddInt2Linear) { AddConst kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2} + {dfcxx::ADD_INT, 2} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); -} \ No newline at end of file +} diff --git a/test/model/dfcxx/idct.cpp b/test/model/dfcxx/idct.cpp index 2a08d1e..b49770b 100644 --- a/test/model/dfcxx/idct.cpp +++ b/test/model/dfcxx/idct.cpp @@ -16,9 +16,9 @@ static const DFOutputPaths nullDevicePath = TEST(DFCxx, IdctAsap) { IDCT kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 1}, - {dfcxx::MUL_INT, 3}, - {dfcxx::SUB_INT, 1} + {dfcxx::ADD_INT, 1}, + {dfcxx::MUL_INT, 3}, + {dfcxx::SUB_INT, 1} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -28,9 +28,9 @@ TEST(DFCxx, IdctAsap) { // TEST(DFCxx, IdctLinear) { // IDCT kernel; // DFLatencyConfig config = { -// {dfcxx::ADD_INT, 1}, -// {dfcxx::MUL_INT, 3}, -// {dfcxx::SUB_INT, 1} +// {dfcxx::ADD_INT, 1}, +// {dfcxx::MUL_INT, 3}, +// {dfcxx::SUB_INT, 1} // }; // EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); // } diff --git a/test/model/dfcxx/matrixmul2.cpp b/test/model/dfcxx/matrixmul2.cpp index 08c7a2b..d2990ea 100644 --- a/test/model/dfcxx/matrixmul2.cpp +++ b/test/model/dfcxx/matrixmul2.cpp @@ -16,8 +16,8 @@ static const DFOutputPaths nullDevicePath = TEST(DFCxx, MatrixMul2AddInt2MulInt3Asap) { MatrixMul2 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 3}, + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 3}, }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -25,8 +25,8 @@ TEST(DFCxx, MatrixMul2AddInt2MulInt3Asap) { TEST(DFCxx, MatrixMul2AddInt2MulInt3Linear) { MatrixMul2 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 2}, + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 2}, }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); -} \ No newline at end of file +} diff --git a/test/model/dfcxx/movingsum.cpp b/test/model/dfcxx/movingsum.cpp index f7e3bd7..c459eef 100644 --- a/test/model/dfcxx/movingsum.cpp +++ b/test/model/dfcxx/movingsum.cpp @@ -16,7 +16,7 @@ static const DFOutputPaths nullDevicePath = TEST(DFCxx, MovingSumAddInt2Asap) { MovingSum kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2} + {dfcxx::ADD_INT, 2} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -24,7 +24,7 @@ TEST(DFCxx, MovingSumAddInt2Asap) { TEST(DFCxx, MovingSumAddInt2Linear) { MovingSum kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2} + {dfcxx::ADD_INT, 2} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); } @@ -32,7 +32,7 @@ TEST(DFCxx, MovingSumAddInt2Linear) { TEST(DFCxx, MovingSumAddInt8Asap) { MovingSum kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 8} + {dfcxx::ADD_INT, 8} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -40,7 +40,7 @@ TEST(DFCxx, MovingSumAddInt8Asap) { TEST(DFCxx, MovingSumAddInt8Linear) { MovingSum kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 8} + {dfcxx::ADD_INT, 8} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); -} \ No newline at end of file +} diff --git a/test/model/dfcxx/muxmul.cpp b/test/model/dfcxx/muxmul.cpp index 195f289..ebb1747 100644 --- a/test/model/dfcxx/muxmul.cpp +++ b/test/model/dfcxx/muxmul.cpp @@ -16,8 +16,8 @@ static const DFOutputPaths nullDevicePath = TEST(DFCxx, MuxMulAddInt2MulInt3Asap) { MuxMul kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 3} + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 3} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -25,8 +25,8 @@ TEST(DFCxx, MuxMulAddInt2MulInt3Asap) { TEST(DFCxx, MuxMulAddInt2MulInt3Linear) { MuxMul kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 3} + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 3} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); } diff --git a/test/model/dfcxx/output_formats.cpp b/test/model/dfcxx/output_formats.cpp new file mode 100644 index 0000000..1cb3787 --- /dev/null +++ b/test/model/dfcxx/output_formats.cpp @@ -0,0 +1,24 @@ +//===----------------------------------------------------------------------===// +// +// Part of the Utopia HLS Project, under the Apache License v2.0 +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2021-2024 ISP RAS (http://www.ispras.ru) +// +//===----------------------------------------------------------------------===// + +#include "polynomial2/polynomial2.h" + +#include "gtest/gtest.h" + +static const Polynomial2 kernel; + +static const DFLatencyConfig config = + {{dfcxx::ADD_INT, 2}, {dfcxx::MUL_INT, 3}}; + +TEST(DFCxxOutputFormats, FIRRTL) { + Polynomial2 kernel; + DFOutputPaths paths = { + {dfcxx::OutputFormatID::SystemVerilog, NULLDEVICE} + }; + EXPECT_EQ(kernel.compile(config, paths, dfcxx::ASAP), true); +} diff --git a/test/model/dfcxx/polynomial2.cpp b/test/model/dfcxx/polynomial2.cpp index 19a4f49..a9aa950 100644 --- a/test/model/dfcxx/polynomial2.cpp +++ b/test/model/dfcxx/polynomial2.cpp @@ -16,8 +16,8 @@ static const DFOutputPaths nullDevicePath = TEST(DFCxx, Polynomial2AddInt2MulInt3Asap) { Polynomial2 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 3} + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 3} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -25,8 +25,8 @@ TEST(DFCxx, Polynomial2AddInt2MulInt3Asap) { TEST(DFCxx, Polynomial2AddInt2MulInt3Linear) { Polynomial2 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 3} + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 3} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); } @@ -34,8 +34,8 @@ TEST(DFCxx, Polynomial2AddInt2MulInt3Linear) { TEST(DFCxx, Polynomial2AddInt8MulInt15Asap) { Polynomial2 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 8}, - {dfcxx::MUL_INT, 15} + {dfcxx::ADD_INT, 8}, + {dfcxx::MUL_INT, 15} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -43,8 +43,8 @@ TEST(DFCxx, Polynomial2AddInt8MulInt15Asap) { TEST(DFCxx, Polynomial2AddInt8MulInt15Linear) { Polynomial2 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 8}, - {dfcxx::MUL_INT, 15} + {dfcxx::ADD_INT, 8}, + {dfcxx::MUL_INT, 15} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); } diff --git a/test/model/dfcxx/scalar3.cpp b/test/model/dfcxx/scalar3.cpp index 3e83607..4dbffe7 100644 --- a/test/model/dfcxx/scalar3.cpp +++ b/test/model/dfcxx/scalar3.cpp @@ -16,8 +16,8 @@ static const DFOutputPaths nullDevicePath = TEST(DFCxx, Scalar3AddInt2MulInt3Asap) { Scalar3 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 3} + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 3} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true); } @@ -25,8 +25,8 @@ TEST(DFCxx, Scalar3AddInt2MulInt3Asap) { TEST(DFCxx, Scalar3AddInt2MulInt3Linear) { Scalar3 kernel; DFLatencyConfig config = { - {dfcxx::ADD_INT, 2}, - {dfcxx::MUL_INT, 3} + {dfcxx::ADD_INT, 2}, + {dfcxx::MUL_INT, 3} }; EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true); } From bd0d2657fdd78a09f6d988ba4b1e1b5eb5a2d3e0 Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Mon, 5 Aug 2024 15:51:16 +0300 Subject: [PATCH 4/5] Fixed misused OutputFormatID. --- test/model/dfcxx/output_formats.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/model/dfcxx/output_formats.cpp b/test/model/dfcxx/output_formats.cpp index 1cb3787..961bfce 100644 --- a/test/model/dfcxx/output_formats.cpp +++ b/test/model/dfcxx/output_formats.cpp @@ -18,7 +18,7 @@ static const DFLatencyConfig config = TEST(DFCxxOutputFormats, FIRRTL) { Polynomial2 kernel; DFOutputPaths paths = { - {dfcxx::OutputFormatID::SystemVerilog, NULLDEVICE} + {dfcxx::OutputFormatID::FIRRTL, NULLDEVICE} }; EXPECT_EQ(kernel.compile(config, paths, dfcxx::ASAP), true); } From 1d20a9c297129787484f4f804fe887b5e10dba6a Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Mon, 5 Aug 2024 16:03:48 +0300 Subject: [PATCH 5/5] Removed Windows-related lines of code according to Pull Request comments. --- src/model/dfcxx/lib/dfcxx/CMakeLists.txt | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/model/dfcxx/lib/dfcxx/CMakeLists.txt b/src/model/dfcxx/lib/dfcxx/CMakeLists.txt index b01cb10..a82e35a 100644 --- a/src/model/dfcxx/lib/dfcxx/CMakeLists.txt +++ b/src/model/dfcxx/lib/dfcxx/CMakeLists.txt @@ -7,13 +7,8 @@ add_subdirectory(varbuilders) ## By default LLVM, MLIR and DFCIR are compiled without RTTI, but not DFCxx. ## So using core Pass functionality from MLIR in converter.cpp causes ## linker-level errors ("undefined reference to `typeinfo for mlir::Pass'"). -## The following lines explicitly disable RTTI for DFCxx. -if (${CMAKE_CXX_COMPILER_ID} STREQUAL "MSVC") - set(DISABLE_RTTI_FLAG "/GR-") -else() - set(DISABLE_RTTI_FLAG "-fno-rtti") -endif() -add_definitions(${DISABLE_RTTI_FLAG}) +## The following line explicitly disables RTTI for DFCxx. +add_definitions("-fno-rtti") set(SOURCES kernel.cpp