From 4df7ae6de32fd3eef604ac09088ba876aa90b0a5 Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 14:21:29 +0300 Subject: [PATCH 1/8] Stubs generation option was added. --- cmake/FindCTemplate.cmake | 42 +++++ config.json | 1 + src/model/dfcir/CMakeLists.txt | 1 + .../include/dfcir/conversions/DFCIRPasses.h | 8 +- .../include/dfcir/conversions/DFCIRPasses.td | 14 ++ src/model/dfcir/lib/dfcir/CMakeLists.txt | 5 + .../lib/dfcir/conversions/CMakeLists.txt | 1 + .../dfcir/conversions/DFCIRPassesUtils.cpp | 7 +- .../conversions/FIRRTLStubsGeneratorPass.cpp | 153 ++++++++++++++++++ src/model/dfcir/templates/stubs.tpl | 45 ++++++ src/model/dfcxx/include/dfcxx/typedefs.h | 1 + src/model/dfcxx/lib/dfcxx/converter.cpp | 8 +- src/options.h | 6 + 13 files changed, 287 insertions(+), 5 deletions(-) create mode 100644 cmake/FindCTemplate.cmake create mode 100644 src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp create mode 100644 src/model/dfcir/templates/stubs.tpl diff --git a/cmake/FindCTemplate.cmake b/cmake/FindCTemplate.cmake new file mode 100644 index 00000000..78ffc27b --- /dev/null +++ b/cmake/FindCTemplate.cmake @@ -0,0 +1,42 @@ +find_path(CTemplate_INCLUDE_DIR "ctemplate/template.h" + PATH_SUFFIXES include) + +if(NOT CTemplate_LIBRARY) + find_library(CTemplate_LIBRARY ctemplate PATH_SUFFIXES lib) +endif() + +if(NOT CTemplate_nothreads_LIBRARY) + find_library(CTemplate_nothreads_LIBRARY ctemplate_nothreads + PATH_SUFFIXES lib) +endif() + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args(CTemplate + REQUIRED_VARS CTemplate_LIBRARY CTemplate_INCLUDE_DIR) + +if(CTemplate_FOUND) + set(CTemplate_INCLUDE_DIRS ${CTemplate_INCLUDE_DIR}) + + if(NOT CTemplate_LIBRARIES) + set(CTemplate_LIBRARIES ${CTemplate_LIBRARY}) + endif() + + if(NOT TARGET CTemplate::CTemplate) + add_library(CTemplate::CTemplate UNKNOWN IMPORTED) + set_target_properties(CTemplate::CTemplate PROPERTIES + INTERFACE_INCLUDE_DIRECTORIES "${CTemplate_INCLUDE_DIRS}" + INTERFACE_LINK_LIBRARIES "$" + IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" + IMPORTED_LOCATION "${CTemplate_LIBRARY}" + ) + endif() + + if((NOT TARGET CTemplate::nothreads) AND (CTemplate_nothreads_LIBRARY)) + add_library(CTemplate::nothreads UNKNOWN IMPORTED) + set_target_properties(CTemplate::nothreads PROPERTIES + INTERFACE_INCLUDE_DIRECTORIES "${CTemplate_INCLUDE_DIRS}" + IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" + IMPORTED_LOCATION "${CTemplate_nothreads_LIBRARY}" + ) + endif() +endif() diff --git a/config.json b/config.json index c66e6961..8d50d751 100644 --- a/config.json +++ b/config.json @@ -4,6 +4,7 @@ "asap_scheduler" : false, "lp_scheduler" : false, "out_sv" : "", + "out_stubs" : "", "out_dfcir" : "", "out_firrtl" : "" } diff --git a/src/model/dfcir/CMakeLists.txt b/src/model/dfcir/CMakeLists.txt index 612caf49..293a8a53 100644 --- a/src/model/dfcir/CMakeLists.txt +++ b/src/model/dfcir/CMakeLists.txt @@ -4,5 +4,6 @@ set(CMAKE_CXX_STANDARD 17) # TODO: Figure out how to pass Tablegen includes the other way. # Issue #15 (https://github.com/ispras/utopia-hls/issues/15). include_directories(${MLIR_INCLUDE_DIRS}) +find_package(CTemplate REQUIRED COMPONENTS nothreads) add_subdirectory(include) add_subdirectory(lib) diff --git a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h index 63973c89..05ae3163 100644 --- a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h +++ b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h @@ -12,6 +12,8 @@ #include "dfcir/DFCIROperations.h" #include "mlir/Pass/Pass.h" +#include "llvm/Support/raw_ostream.h" + #include "memory" namespace mlir::dfcir { @@ -65,15 +67,15 @@ namespace mlir::dfcir { using std::unique_ptr; using mlir::Pass; -unique_ptr createDFCIRToFIRRTLPass(LatencyConfig *config = nullptr); +unique_ptr createDFCIRToFIRRTLPass(LatencyConfig *config); unique_ptr createDFCIRASAPSchedulerPass(); unique_ptr createDFCIRLinearSchedulerPass(); -} // namespace mlir::dfcir +unique_ptr createFIRRTLStubGeneratorPass(llvm::raw_ostream *stream); -#define GEN_PASS_REGISTRATION +} // namespace mlir::dfcir #include "dfcir/conversions/DFCIRPasses.h.inc" diff --git a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td index 660254d3..a1ac8124 100644 --- a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td +++ b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td @@ -37,4 +37,18 @@ def DFCIRLinearSchedulerPass: Pass<"dfcir-linear-scheduler-pass", "mlir::ModuleO let constructor = "mlir::dfcir::createDFCIRLinearSchedulerPass()"; } +def FIRRTLStubGeneratorPass: Pass<"firrtl-stub-generator-pass", "mlir::ModuleOp"> { + let summary = "Generate stubs for pipelined computational modules, specified in FIRRTL."; + + let options = [ + Option<"stream", + "stream", + "llvm::raw_ostream *", + "nullptr", + "Stream to dump stubs to."> + ]; + + let constructor = "mlir::dfcir::createFIRRTLStubGeneratorPass()"; +} + #endif // DFCIR_Passes diff --git a/src/model/dfcir/lib/dfcir/CMakeLists.txt b/src/model/dfcir/lib/dfcir/CMakeLists.txt index cdefb327..e2beb4ba 100644 --- a/src/model/dfcir/lib/dfcir/CMakeLists.txt +++ b/src/model/dfcir/lib/dfcir/CMakeLists.txt @@ -19,6 +19,10 @@ target_include_directories(MLIRDFCIR ## Issue #16 (https://github.com/ispras/utopia-hls/issues/16). ) +set(TEMPLATES_PATH "${PROJECT_SOURCE_DIR}/templates") + +add_compile_definitions(TEMPLATES_PATH="${TEMPLATES_PATH}" STUBS_TEMPLATE_PATH="${TEMPLATES_PATH}/stubs.tpl") + target_link_libraries(MLIRDFCIR PUBLIC MLIRIR @@ -29,6 +33,7 @@ target_link_libraries(MLIRDFCIR PRIVATE LpSolve::LpSolve + CTemplate::nothreads ) add_library(Utopia::MLIRDFCIR ALIAS MLIRDFCIR) diff --git a/src/model/dfcir/lib/dfcir/conversions/CMakeLists.txt b/src/model/dfcir/lib/dfcir/conversions/CMakeLists.txt index 57a9d460..399f09a5 100644 --- a/src/model/dfcir/lib/dfcir/conversions/CMakeLists.txt +++ b/src/model/dfcir/lib/dfcir/conversions/CMakeLists.txt @@ -3,6 +3,7 @@ set(PASSES conversions/DFCIRASAPSchedulerPass.cpp conversions/DFCIRLinearSchedulerPass.cpp conversions/DFCIRLPUtils.cpp + conversions/FIRRTLStubsGeneratorPass.cpp ) set(CONV_LIBS diff --git a/src/model/dfcir/lib/dfcir/conversions/DFCIRPassesUtils.cpp b/src/model/dfcir/lib/dfcir/conversions/DFCIRPassesUtils.cpp index 0a17e9ff..d19c236f 100644 --- a/src/model/dfcir/lib/dfcir/conversions/DFCIRPassesUtils.cpp +++ b/src/model/dfcir/lib/dfcir/conversions/DFCIRPassesUtils.cpp @@ -32,7 +32,9 @@ inline FExtModuleOp createBufferModule(OpBuilder &builder, auto typeWidth = circt::firrtl::getBitWidth(llvm::dyn_cast(type)); assert(typeWidth.has_value()); - return builder.create( + IntegerType attrType = mlir::IntegerType::get(builder.getContext(), 32, + mlir::IntegerType::Unsigned); + auto module = builder.create( loc, mlir::StringAttr::get(builder.getContext(), name), circt::firrtl::ConventionAttr::get(builder.getContext(), @@ -40,6 +42,9 @@ inline FExtModuleOp createBufferModule(OpBuilder &builder, ports, StringRef(name), mlir::ArrayAttr()); + module->setAttr(INSTANCE_LATENCY_ATTR, + mlir::IntegerAttr::get(attrType, stages)); + return module; } inline FExtModuleOp createBufferModuleWithTypeName(OpBuilder &builder, diff --git a/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp b/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp new file mode 100644 index 00000000..b791557e --- /dev/null +++ b/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp @@ -0,0 +1,153 @@ +//===----------------------------------------------------------------------===// +// +// Part of the Utopia HLS Project, under the Apache License v2.0 +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2021-2024 ISP RAS (http://www.ispras.ru) +// +//===----------------------------------------------------------------------===// + +#include "dfcir/conversions/DFCIRPasses.h" +#include "dfcir/conversions/DFCIRPassesUtils.h" + +#include "circt/Dialect/FIRRTL/FIRRTLDialect.h" +#include "circt/Dialect/FIRRTL/FIRRTLOps.h" +#include "circt/Dialect/FIRRTL/FIRRTLTypes.h" +#include "ctemplate/template.h" +#include "mlir/IR/BuiltinOps.h" + +#include +#include + +namespace mlir::dfcir { + +#define GEN_PASS_DECL_FIRRTLSTUBGENERATORPASS +#define GEN_PASS_DEF_FIRRTLSTUBGENERATORPASS + +#include "dfcir/conversions/DFCIRPasses.h.inc" + +class FIRRTLStubGeneratorPass + : public impl::FIRRTLStubGeneratorPassBase { + using TemplateDictionary = ctemplate::TemplateDictionary; + using FExtModuleOp = circt::firrtl::FExtModuleOp; + using CircuitOp = circt::firrtl::CircuitOp; + using FIRRTLBaseType = circt::firrtl::FIRRTLBaseType; + using IntType = circt::firrtl::IntType; + +private: + TemplateDictionary *processFIFOModule(TemplateDictionary *dict, + FExtModuleOp module) { + TemplateDictionary *result = dict->AddSectionDictionary("FIFO_MODULES"); + auto ports = module.getPorts(); + auto res1Type = llvm::cast(module.getPortType(0)); + int32_t width = res1Type.getBitWidthOrSentinel(); + result->SetFormattedValue("WIDTH", "%d", width - 1); + result->SetValue("RES1", ports[0].getName().data()); + result->SetValue("ARG1", ports[1].getName().data()); + result->SetValue("CLK", ports[2].getName().data()); + return result; + } + + TemplateDictionary *processBinModule(TemplateDictionary *dict, + FExtModuleOp module, + unsigned latency) { + TemplateDictionary *result = dict->AddSectionDictionary("BINARY_MODULES"); + auto moduleName = module.getModuleName(); + if (moduleName.contains(ADD_MODULE)) { + result->SetValue("OP", "+"); + } else if (moduleName.contains(SUB_MODULE)) { + result->SetValue("OP", "-"); + } else { + result->SetValue("OP", "*"); + } + auto ports = module.getPorts(); + auto res1Type = llvm::cast(module.getPortType(0)); + bool isSigned = llvm::cast(res1Type).isSigned(); + int32_t width3 = res1Type.getBitWidthOrSentinel(); + result->SetFormattedValue("WIDTH3", "%d", width3 - 1); + auto arg1Type = llvm::cast(module.getPortType(1)); + int32_t width1 = arg1Type.getBitWidthOrSentinel(); + result->SetFormattedValue("WIDTH1", "%d", width1 - 1); + auto arg2Type = llvm::cast(module.getPortType(2)); + int32_t width2 = arg2Type.getBitWidthOrSentinel(); + result->SetFormattedValue("WIDTH2", "%d", width2 - 1); + int32_t rWidth = std::max(width1, width2); + result->SetFormattedValue("RWIDTH", "%d", rWidth - 1); + result->SetValue("RES1", ports[0].getName().data()); + auto arg1 = ports[1].getName().data(); + result->SetValue("ARG1", arg1); + auto arg2 = ports[2].getName().data(); + result->SetValue("ARG2", arg2); + result->SetValue("CLK", ports[3].getName().data()); + int32_t repeat1 = std::max(rWidth - width1, 0); + result->SetFormattedValue("REPEAT1", "%d", repeat1); + int32_t repeat2 = std::max(rWidth - width2, 0); + result->SetFormattedValue("REPEAT2", "%d", repeat2); + int32_t repeat3 = std::max(width3 - rWidth, 0); + result->SetFormattedValue("REPEAT3", "%d", repeat3); + int32_t diff = std::min(width3, rWidth); + result->SetFormattedValue("DIFF", "%d", diff - 1); + int32_t cat = std::max(width3, rWidth); + result->SetFormattedValue("CAT", "%d", cat - 1); + if (isSigned) { + result->SetFormattedValue("REPEAT_VAL1", "%s[%d]", arg1, width1 - 1); + result->SetFormattedValue("REPEAT_VAL2", "%s[%d]", arg2, width2 - 1); + result->SetFormattedValue("REPEAT_VAL3", "r[%d][%d]", + latency - 1, rWidth - 1); + } else { + result->SetValue("REPEAT_VAL1", "1'h0"); + result->SetValue("REPEAT_VAL2", "1'h0"); + result->SetValue("REPEAT_VAL3", "1'h0"); + } + return result; + } + + void fillDictionary(TemplateDictionary *dict, CircuitOp circuit) { + Block *block = circuit.getBodyBlock(); + auto begin = block->op_begin(); + auto end = block->op_end(); + for (auto op = begin; op != end; ++op) { + auto moduleName = (*op).getModuleName(); + unsigned latency = + (*op)->getAttr(INSTANCE_LATENCY_ATTR) + .cast().getUInt(); + TemplateDictionary *moduleDict = + moduleName.contains(BUF_MODULE) ? + processFIFOModule(dict, *op) : + processBinModule(dict, *op, latency); + moduleDict->SetFormattedValue("LATENCY", "%u", latency - 1); + moduleDict->SetValue("MODULE_NAME", moduleName.data()); + } + } + + std::string generateOutput() { + std::string result; + TemplateDictionary *topLevelDict = new TemplateDictionary("stubs"); + + mlir::Operation *op = getOperation(); + CircuitOp circuit = mlir::utils::findFirstOccurence(op); + + fillDictionary(topLevelDict, circuit); + ctemplate::ExpandTemplate(STUBS_TEMPLATE_PATH, ctemplate::DO_NOT_STRIP, + topLevelDict, &result); + return result; + } + +public: + explicit FIRRTLStubGeneratorPass(const FIRRTLStubGeneratorPassOptions &opt) + : impl::FIRRTLStubGeneratorPassBase(opt) {} + + void runOnOperation() override { + const std::string &output = generateOutput(); + + *stream << output; + } +}; + +std::unique_ptr + createFIRRTLStubGeneratorPass(llvm::raw_ostream *stream) { + FIRRTLStubGeneratorPassOptions options; + options.stream = stream; + return std::make_unique(options); +} + +} // namespace mlir::dfcir diff --git a/src/model/dfcir/templates/stubs.tpl b/src/model/dfcir/templates/stubs.tpl new file mode 100644 index 00000000..e7051263 --- /dev/null +++ b/src/model/dfcir/templates/stubs.tpl @@ -0,0 +1,45 @@ +{{#LICENSE}} +{{!===---------------------------------------------------------------------===}} +{{! }} +{{! Part of the Utopia HLS Project, under the Apache License v2.0 }} +{{! SPDX-License-Identifier: Apache-2.0 }} +{{! Copyright 2021-2024 ISP RAS (http://www.ispras.ru) }} +{{! }} +{{!===---------------------------------------------------------------------===}} +{{/LICENSE}} +// This file has been automatically generated by Utopia HLS. + +{{#FIFO_MODULES}}module {{MODULE_NAME}} ( +input [{{WIDTH}}:0] {{ARG1}}, output [{{WIDTH}}:0] {{RES1}}, input {{CLK}}); + + reg [{{WIDTH}}:0] r[{{LATENCY}}:0]; + + integer i; + always @ (posedge {{CLK}}) begin + for (i = {{LATENCY}}; i != 0; i = i - 1) begin + r[i] <= r[i - 1]; + end + r[0] <= {{ARG1}}; + end + assign {{RES1}} = r[{{LATENCY}}]; +endmodule // {{MODULE_NAME}} + +{{/FIFO_MODULES}} +{{#BINARY_MODULES}}module {{MODULE_NAME}} ( +input [{{WIDTH1}}:0] {{ARG1}}, input [{{WIDTH2}}:0] {{ARG2}}, output [{{WIDTH3}}:0] {{RES1}}, input {{CLK}}); + + reg [{{RWIDTH}}:0] r[{{LATENCY}}:0]; + reg [{{CAT}}:0] cat; + + integer i; + always @ (posedge {{CLK}}) begin + for (i = {{LATENCY}}; i != 0; i = i - 1) begin + r[i] <= r[i - 1]; + end + r[0] <= {{{{REPEAT1}}{{{REPEAT_VAL1}}}}, {{ARG1}}} {{OP}} {{{{REPEAT2}}{{{REPEAT_VAL2}}}}, {{ARG2}}}; + end + assign cat = {{{{REPEAT3}}{{{REPEAT_VAL3}}}}, r[{{LATENCY}}]}; + assign {{RES1}} = cat[{{DIFF}}:0]; +endmodule // {{MODULE_NAME}} + +{{/BINARY_MODULES}} diff --git a/src/model/dfcxx/include/dfcxx/typedefs.h b/src/model/dfcxx/include/dfcxx/typedefs.h index c3133492..6636763e 100644 --- a/src/model/dfcxx/include/dfcxx/typedefs.h +++ b/src/model/dfcxx/include/dfcxx/typedefs.h @@ -62,6 +62,7 @@ enum Scheduler { // Used for accessing specified output format paths. enum class OutputFormatID : uint8_t { SystemVerilog = 0, + Stubs, DFCIR, FIRRTL, // Utility value. Constains the number of elements in the enum. diff --git a/src/model/dfcxx/lib/dfcxx/converter.cpp b/src/model/dfcxx/lib/dfcxx/converter.cpp index c43d8d66..42397515 100644 --- a/src/model/dfcxx/lib/dfcxx/converter.cpp +++ b/src/model/dfcxx/lib/dfcxx/converter.cpp @@ -73,7 +73,13 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module, pm.addPass(createDFCIRDumperPass(stream)); } - // Add FIRRTL->SystemVerilog passes if SystemVerilog output option is specified. + // Add stub generation pass if the corresponding option is specified. + if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(Stubs)]) { + pm.addPass(mlir::dfcir::createFIRRTLStubGeneratorPass(stream)); + } + + // Add FIRRTL->SystemVerilog passes if SystemVerilog output + // option is specified. if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(SystemVerilog)]) { pm.addPass(circt::createLowerFIRRTLToHWPass()); pm.addPass(circt::createLowerSeqToSVPass()); diff --git a/src/options.h b/src/options.h index fc7c1720..0d400f5f 100644 --- a/src/options.h +++ b/src/options.h @@ -36,6 +36,7 @@ #define ASAP_SCHEDULER_JSON "asap_scheduler" #define LP_SCHEDULER_JSON "lp_scheduler" #define OUT_SV_JSON "out_sv" +#define OUT_STUBS_JSON "out_stubs" #define OUT_DFCIR_JSON "out_dfcir" #define OUT_FIRRTL_JSON "out_firrtl" @@ -49,6 +50,7 @@ #define LP_SCHEDULER_FLAG CLI_FLAG("l") #define OUTPUT_GROUP "output" #define OUT_SV_ARG CLI_ARG("out-sv") +#define OUT_STUBS_ARG CLI_ARG("out-stubs") #define OUT_DFCIR_ARG CLI_ARG("out-dfcir") #define OUT_FIRRTL_ARG CLI_ARG("out-firrtl") @@ -184,6 +186,9 @@ struct HlsOptions final : public AppOptions { outputGroup->add_option(OUT_SV_ARG, outNames[OUT_FORMAT_ID_INT(SystemVerilog)], "Path to output the SystemVerilog module"); + outputGroup->add_option(OUT_STUBS_ARG, + outNames[OUT_FORMAT_ID_INT(Stubs)], + "Path to output stubs for SystemVerilog modules"); outputGroup->add_option(OUT_DFCIR_ARG, outNames[OUT_FORMAT_ID_INT(DFCIR)], "Path to output unscheduled DFCIR"); @@ -198,6 +203,7 @@ struct HlsOptions final : public AppOptions { get(json, ASAP_SCHEDULER_JSON, asapScheduler); get(json, LP_SCHEDULER_JSON, lpScheduler); get(json, OUT_SV_JSON, outNames[OUT_FORMAT_ID_INT(SystemVerilog)]); + get(json, OUT_STUBS_JSON, outNames[OUT_FORMAT_ID_INT(Stubs)]); get(json, OUT_DFCIR_JSON, outNames[OUT_FORMAT_ID_INT(DFCIR)]); get(json, OUT_FIRRTL_JSON, outNames[OUT_FORMAT_ID_INT(FIRRTL)]); } From e56ef7751d758efe4cd2ce13f5549fa2d8e7dee6 Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 14:26:14 +0300 Subject: [PATCH 2/8] Fixed README.md . --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 11fafe5c..a67bf31e 100644 --- a/README.md +++ b/README.md @@ -217,6 +217,7 @@ The list of arguments for `hls`-mode is presented below: * `-h,--help`: *optional* flag; used to print the help-message about other arguments. * `--config `: *required* filesystem-path option; used to specify the file for a JSON latency configuration file. Its format is presented in *JSON Configuration* section. * `--out-sv `: *optional* filesystem-path option; used to specify the output SystemVerilog file. +* `--out-stubs `: *optional* filesystem-path option; used to specify the output file for generated SystemVerilog stubs. * `--out-dfcir `: *optional* filesystem-path option; used to specify the output DFCIR file. * `--out-firrtl `: *optional* filesystem-path option; used to specify the output FIRRTL file. * `-a` or `-l`: *required* flag; used to specify the chosen scheduling strategy - either as-soon-as-possible or linear programming. **Exactly one of these flags has to be specified**. From a82a81ac76379c1ec57b536020dd9618980e7e6e Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 14:35:27 +0300 Subject: [PATCH 3/8] Fix README.md and CI regarding CTemplate. --- .github/workflows/main.yml | 2 +- README.md | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index b7a46487..c67c60e6 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -30,7 +30,7 @@ jobs: - name: Download APT dependencies run: | sudo apt update - sudo apt install build-essential clang cmake g++ gcc liblpsolve55-dev lld make ninja-build + sudo apt install build-essential clang cmake g++ gcc liblpsolve55-dev lld make ninja-build libctemplate-dev - name: Download and configure CIRCT & LLVM env: diff --git a/README.md b/README.md index a67bf31e..4aa08eb2 100644 --- a/README.md +++ b/README.md @@ -63,11 +63,12 @@ It is recommended to use Utopia HLS on Debian-based operating systems (e.g. Ubun * `cmake` ver. 3.20.0 or higher (*) * `liblpsolve55-dev` * `ninja-build` (preferred) or `make` +* `libctemplate-dev` as a template generator for SystemVerilog stubs The following command can be used to install all of these dependencies regardless of what exactly will be used to compile Utopia HLS: ```bash -sudo apt install build-essential clang cmake g++ gcc liblpsolve55-dev lld make ninja-build +sudo apt install build-essential clang cmake g++ gcc liblpsolve55-dev lld make ninja-build libctemplate-dev ``` (*)**Note**: in case `cmake` which was installed from `apt install` has a version lower than 3.20.0, follow this [guide](https://apt.kitware.com/) and use `sudo apt install cmake` again. From e277952bc224cf66412e8c98694b27c136eb0b4b Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 16:33:41 +0300 Subject: [PATCH 4/8] Recently discussed CLI & template fixes. --- README.md | 2 +- config.json | 2 +- .../dfcir/conversions/FIRRTLStubsGeneratorPass.cpp | 11 +++++++++++ src/model/dfcir/templates/stubs.tpl | 10 +++------- src/model/dfcxx/include/dfcxx/typedefs.h | 2 +- src/model/dfcxx/lib/dfcxx/converter.cpp | 2 +- src/options.h | 10 +++++----- 7 files changed, 23 insertions(+), 16 deletions(-) diff --git a/README.md b/README.md index 4aa08eb2..4219d05b 100644 --- a/README.md +++ b/README.md @@ -218,7 +218,7 @@ The list of arguments for `hls`-mode is presented below: * `-h,--help`: *optional* flag; used to print the help-message about other arguments. * `--config `: *required* filesystem-path option; used to specify the file for a JSON latency configuration file. Its format is presented in *JSON Configuration* section. * `--out-sv `: *optional* filesystem-path option; used to specify the output SystemVerilog file. -* `--out-stubs `: *optional* filesystem-path option; used to specify the output file for generated SystemVerilog stubs. +* `--out-sv-stubs `: *optional* filesystem-path option; used to specify the output file for generated SystemVerilog stubs. * `--out-dfcir `: *optional* filesystem-path option; used to specify the output DFCIR file. * `--out-firrtl `: *optional* filesystem-path option; used to specify the output FIRRTL file. * `-a` or `-l`: *required* flag; used to specify the chosen scheduling strategy - either as-soon-as-possible or linear programming. **Exactly one of these flags has to be specified**. diff --git a/config.json b/config.json index 8d50d751..790a4f05 100644 --- a/config.json +++ b/config.json @@ -4,7 +4,7 @@ "asap_scheduler" : false, "lp_scheduler" : false, "out_sv" : "", - "out_stubs" : "", + "out_sv_stubs" : "", "out_dfcir" : "", "out_firrtl" : "" } diff --git a/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp b/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp index b791557e..26528fb7 100644 --- a/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp +++ b/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp @@ -16,6 +16,7 @@ #include "mlir/IR/BuiltinOps.h" #include +#include #include namespace mlir::dfcir { @@ -117,6 +118,16 @@ class FIRRTLStubGeneratorPass moduleDict->SetFormattedValue("LATENCY", "%u", latency - 1); moduleDict->SetValue("MODULE_NAME", moduleName.data()); } + auto time = std::time(nullptr); + auto *localTime = std::localtime(&time); + dict->SetFormattedValue("GEN_TIME", + "%d-%d-%d %d:%d:%d", + localTime->tm_mday, + localTime->tm_mon + 1, + localTime->tm_year + 1900, + localTime->tm_hour, + localTime->tm_min, + localTime->tm_sec); } std::string generateOutput() { diff --git a/src/model/dfcir/templates/stubs.tpl b/src/model/dfcir/templates/stubs.tpl index e7051263..d17cc929 100644 --- a/src/model/dfcir/templates/stubs.tpl +++ b/src/model/dfcir/templates/stubs.tpl @@ -7,11 +7,9 @@ {{! }} {{!===---------------------------------------------------------------------===}} {{/LICENSE}} -// This file has been automatically generated by Utopia HLS. - -{{#FIFO_MODULES}}module {{MODULE_NAME}} ( -input [{{WIDTH}}:0] {{ARG1}}, output [{{WIDTH}}:0] {{RES1}}, input {{CLK}}); +// This file has been automatically generated by Utopia HLS at {{GEN_TIME}}. +{{#FIFO_MODULES}}module {{MODULE_NAME}} (input [{{WIDTH}}:0] {{ARG1}}, output [{{WIDTH}}:0] {{RES1}}, input {{CLK}}); reg [{{WIDTH}}:0] r[{{LATENCY}}:0]; integer i; @@ -25,9 +23,7 @@ input [{{WIDTH}}:0] {{ARG1}}, output [{{WIDTH}}:0] {{RES1}}, input {{CLK}}); endmodule // {{MODULE_NAME}} {{/FIFO_MODULES}} -{{#BINARY_MODULES}}module {{MODULE_NAME}} ( -input [{{WIDTH1}}:0] {{ARG1}}, input [{{WIDTH2}}:0] {{ARG2}}, output [{{WIDTH3}}:0] {{RES1}}, input {{CLK}}); - +{{#BINARY_MODULES}}module {{MODULE_NAME}} (input [{{WIDTH1}}:0] {{ARG1}}, input [{{WIDTH2}}:0] {{ARG2}}, output [{{WIDTH3}}:0] {{RES1}}, input {{CLK}}); reg [{{RWIDTH}}:0] r[{{LATENCY}}:0]; reg [{{CAT}}:0] cat; diff --git a/src/model/dfcxx/include/dfcxx/typedefs.h b/src/model/dfcxx/include/dfcxx/typedefs.h index 6636763e..7f1795ad 100644 --- a/src/model/dfcxx/include/dfcxx/typedefs.h +++ b/src/model/dfcxx/include/dfcxx/typedefs.h @@ -62,7 +62,7 @@ enum Scheduler { // Used for accessing specified output format paths. enum class OutputFormatID : uint8_t { SystemVerilog = 0, - Stubs, + SVStubs, DFCIR, FIRRTL, // Utility value. Constains the number of elements in the enum. diff --git a/src/model/dfcxx/lib/dfcxx/converter.cpp b/src/model/dfcxx/lib/dfcxx/converter.cpp index 42397515..a0c48863 100644 --- a/src/model/dfcxx/lib/dfcxx/converter.cpp +++ b/src/model/dfcxx/lib/dfcxx/converter.cpp @@ -74,7 +74,7 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module, } // Add stub generation pass if the corresponding option is specified. - if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(Stubs)]) { + if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(SVStubs)]) { pm.addPass(mlir::dfcir::createFIRRTLStubGeneratorPass(stream)); } diff --git a/src/options.h b/src/options.h index 0d400f5f..cf9c57ea 100644 --- a/src/options.h +++ b/src/options.h @@ -36,7 +36,7 @@ #define ASAP_SCHEDULER_JSON "asap_scheduler" #define LP_SCHEDULER_JSON "lp_scheduler" #define OUT_SV_JSON "out_sv" -#define OUT_STUBS_JSON "out_stubs" +#define OUT_SV_STUBS_JSON "out_sv_stubs" #define OUT_DFCIR_JSON "out_dfcir" #define OUT_FIRRTL_JSON "out_firrtl" @@ -50,7 +50,7 @@ #define LP_SCHEDULER_FLAG CLI_FLAG("l") #define OUTPUT_GROUP "output" #define OUT_SV_ARG CLI_ARG("out-sv") -#define OUT_STUBS_ARG CLI_ARG("out-stubs") +#define OUT_SV_STUBS_ARG CLI_ARG("out-sv-stubs") #define OUT_DFCIR_ARG CLI_ARG("out-dfcir") #define OUT_FIRRTL_ARG CLI_ARG("out-firrtl") @@ -186,8 +186,8 @@ struct HlsOptions final : public AppOptions { outputGroup->add_option(OUT_SV_ARG, outNames[OUT_FORMAT_ID_INT(SystemVerilog)], "Path to output the SystemVerilog module"); - outputGroup->add_option(OUT_STUBS_ARG, - outNames[OUT_FORMAT_ID_INT(Stubs)], + outputGroup->add_option(OUT_SV_STUBS_ARG, + outNames[OUT_FORMAT_ID_INT(SVStubs)], "Path to output stubs for SystemVerilog modules"); outputGroup->add_option(OUT_DFCIR_ARG, outNames[OUT_FORMAT_ID_INT(DFCIR)], @@ -203,7 +203,7 @@ struct HlsOptions final : public AppOptions { get(json, ASAP_SCHEDULER_JSON, asapScheduler); get(json, LP_SCHEDULER_JSON, lpScheduler); get(json, OUT_SV_JSON, outNames[OUT_FORMAT_ID_INT(SystemVerilog)]); - get(json, OUT_STUBS_JSON, outNames[OUT_FORMAT_ID_INT(Stubs)]); + get(json, OUT_SV_STUBS_JSON, outNames[OUT_FORMAT_ID_INT(SVStubs)]); get(json, OUT_DFCIR_JSON, outNames[OUT_FORMAT_ID_INT(DFCIR)]); get(json, OUT_FIRRTL_JSON, outNames[OUT_FORMAT_ID_INT(FIRRTL)]); } From bf18bbc9d8e3232ab36969a57b3bbb2b08a234ed Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 17:56:37 +0300 Subject: [PATCH 5/8] Fixes according to Pull Request commits; error and memory handling for StubGenerator was added. --- README.md | 2 +- config.json | 2 +- .../include/dfcir/conversions/DFCIRPasses.td | 2 +- .../conversions/FIRRTLStubsGeneratorPass.cpp | 44 +++++++++++++------ src/model/dfcir/templates/stubs.tpl | 2 +- src/model/dfcxx/include/dfcxx/typedefs.h | 2 +- src/model/dfcxx/lib/dfcxx/converter.cpp | 5 ++- src/options.h | 12 ++--- 8 files changed, 44 insertions(+), 27 deletions(-) diff --git a/README.md b/README.md index 4219d05b..8cec3a05 100644 --- a/README.md +++ b/README.md @@ -218,7 +218,7 @@ The list of arguments for `hls`-mode is presented below: * `-h,--help`: *optional* flag; used to print the help-message about other arguments. * `--config `: *required* filesystem-path option; used to specify the file for a JSON latency configuration file. Its format is presented in *JSON Configuration* section. * `--out-sv `: *optional* filesystem-path option; used to specify the output SystemVerilog file. -* `--out-sv-stubs `: *optional* filesystem-path option; used to specify the output file for generated SystemVerilog stubs. +* `--out-sv-lib `: *optional* filesystem-path option; used to specify the output SystemVerilog file for generated operations library. * `--out-dfcir `: *optional* filesystem-path option; used to specify the output DFCIR file. * `--out-firrtl `: *optional* filesystem-path option; used to specify the output FIRRTL file. * `-a` or `-l`: *required* flag; used to specify the chosen scheduling strategy - either as-soon-as-possible or linear programming. **Exactly one of these flags has to be specified**. diff --git a/config.json b/config.json index 790a4f05..41425927 100644 --- a/config.json +++ b/config.json @@ -4,7 +4,7 @@ "asap_scheduler" : false, "lp_scheduler" : false, "out_sv" : "", - "out_sv_stubs" : "", + "out_sv_lib" : "", "out_dfcir" : "", "out_firrtl" : "" } diff --git a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td index a1ac8124..dda21fb7 100644 --- a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td +++ b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.td @@ -38,7 +38,7 @@ def DFCIRLinearSchedulerPass: Pass<"dfcir-linear-scheduler-pass", "mlir::ModuleO } def FIRRTLStubGeneratorPass: Pass<"firrtl-stub-generator-pass", "mlir::ModuleOp"> { - let summary = "Generate stubs for pipelined computational modules, specified in FIRRTL."; + let summary = "Generate stub modules for pipelined computational operations."; let options = [ Option<"stream", diff --git a/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp b/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp index 26528fb7..9f71790e 100644 --- a/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp +++ b/src/model/dfcir/lib/dfcir/conversions/FIRRTLStubsGeneratorPass.cpp @@ -2,7 +2,7 @@ // // Part of the Utopia HLS Project, under the Apache License v2.0 // SPDX-License-Identifier: Apache-2.0 -// Copyright 2021-2024 ISP RAS (http://www.ispras.ru) +// Copyright 2024 ISP RAS (http://www.ispras.ru) // //===----------------------------------------------------------------------===// @@ -17,6 +17,7 @@ #include #include +#include #include namespace mlir::dfcir { @@ -57,8 +58,11 @@ class FIRRTLStubGeneratorPass result->SetValue("OP", "+"); } else if (moduleName.contains(SUB_MODULE)) { result->SetValue("OP", "-"); - } else { + } else if (moduleName.contains(MUL_MODULE)) { result->SetValue("OP", "*"); + } else { + module.emitError("Unsupported binary operation."); + return nullptr; } auto ports = module.getPorts(); auto res1Type = llvm::cast(module.getPortType(0)); @@ -90,19 +94,19 @@ class FIRRTLStubGeneratorPass int32_t cat = std::max(width3, rWidth); result->SetFormattedValue("CAT", "%d", cat - 1); if (isSigned) { - result->SetFormattedValue("REPEAT_VAL1", "%s[%d]", arg1, width1 - 1); - result->SetFormattedValue("REPEAT_VAL2", "%s[%d]", arg2, width2 - 1); - result->SetFormattedValue("REPEAT_VAL3", "r[%d][%d]", - latency - 1, rWidth - 1); + result->SetFormattedValue("REPEAT_VAL1", "%s[%d]", arg1, width1 - 1); + result->SetFormattedValue("REPEAT_VAL2", "%s[%d]", arg2, width2 - 1); + result->SetFormattedValue("REPEAT_VAL3", "r[%d][%d]", + latency - 1, rWidth - 1); } else { - result->SetValue("REPEAT_VAL1", "1'h0"); - result->SetValue("REPEAT_VAL2", "1'h0"); - result->SetValue("REPEAT_VAL3", "1'h0"); + result->SetValue("REPEAT_VAL1", "1'h0"); + result->SetValue("REPEAT_VAL2", "1'h0"); + result->SetValue("REPEAT_VAL3", "1'h0"); } return result; } - void fillDictionary(TemplateDictionary *dict, CircuitOp circuit) { + LogicalResult fillDictionary(TemplateDictionary *dict, CircuitOp circuit) { Block *block = circuit.getBodyBlock(); auto begin = block->op_begin(); auto end = block->op_end(); @@ -115,6 +119,9 @@ class FIRRTLStubGeneratorPass moduleName.contains(BUF_MODULE) ? processFIFOModule(dict, *op) : processBinModule(dict, *op, latency); + if (!moduleDict) { + return failure(); + } moduleDict->SetFormattedValue("LATENCY", "%u", latency - 1); moduleDict->SetValue("MODULE_NAME", moduleName.data()); } @@ -128,18 +135,23 @@ class FIRRTLStubGeneratorPass localTime->tm_hour, localTime->tm_min, localTime->tm_sec); + return success(); } - std::string generateOutput() { + std::optional generateOutput() { std::string result; TemplateDictionary *topLevelDict = new TemplateDictionary("stubs"); mlir::Operation *op = getOperation(); CircuitOp circuit = mlir::utils::findFirstOccurence(op); - fillDictionary(topLevelDict, circuit); + if (failed(fillDictionary(topLevelDict, circuit))) { + delete topLevelDict; + return {}; + } ctemplate::ExpandTemplate(STUBS_TEMPLATE_PATH, ctemplate::DO_NOT_STRIP, topLevelDict, &result); + delete topLevelDict; return result; } @@ -148,9 +160,13 @@ class FIRRTLStubGeneratorPass : impl::FIRRTLStubGeneratorPassBase(opt) {} void runOnOperation() override { - const std::string &output = generateOutput(); + auto outputOrError = generateOutput(); + + if (!outputOrError) { + return signalPassFailure(); + } - *stream << output; + *stream << *outputOrError; } }; diff --git a/src/model/dfcir/templates/stubs.tpl b/src/model/dfcir/templates/stubs.tpl index d17cc929..f1ab59e0 100644 --- a/src/model/dfcir/templates/stubs.tpl +++ b/src/model/dfcir/templates/stubs.tpl @@ -3,7 +3,7 @@ {{! }} {{! Part of the Utopia HLS Project, under the Apache License v2.0 }} {{! SPDX-License-Identifier: Apache-2.0 }} -{{! Copyright 2021-2024 ISP RAS (http://www.ispras.ru) }} +{{! Copyright 2024 ISP RAS (http://www.ispras.ru) }} {{! }} {{!===---------------------------------------------------------------------===}} {{/LICENSE}} diff --git a/src/model/dfcxx/include/dfcxx/typedefs.h b/src/model/dfcxx/include/dfcxx/typedefs.h index 7f1795ad..250add75 100644 --- a/src/model/dfcxx/include/dfcxx/typedefs.h +++ b/src/model/dfcxx/include/dfcxx/typedefs.h @@ -62,7 +62,7 @@ enum Scheduler { // Used for accessing specified output format paths. enum class OutputFormatID : uint8_t { SystemVerilog = 0, - SVStubs, + SVLibrary, DFCIR, FIRRTL, // Utility value. Constains the number of elements in the enum. diff --git a/src/model/dfcxx/lib/dfcxx/converter.cpp b/src/model/dfcxx/lib/dfcxx/converter.cpp index a0c48863..714a8e23 100644 --- a/src/model/dfcxx/lib/dfcxx/converter.cpp +++ b/src/model/dfcxx/lib/dfcxx/converter.cpp @@ -73,8 +73,9 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module, pm.addPass(createDFCIRDumperPass(stream)); } - // Add stub generation pass if the corresponding option is specified. - if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(SVStubs)]) { + // Add SystemVerilog library generation pass if the corresponding option + // is specified. + if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(SVLibrary)]) { pm.addPass(mlir::dfcir::createFIRRTLStubGeneratorPass(stream)); } diff --git a/src/options.h b/src/options.h index cf9c57ea..1ad7e612 100644 --- a/src/options.h +++ b/src/options.h @@ -36,7 +36,7 @@ #define ASAP_SCHEDULER_JSON "asap_scheduler" #define LP_SCHEDULER_JSON "lp_scheduler" #define OUT_SV_JSON "out_sv" -#define OUT_SV_STUBS_JSON "out_sv_stubs" +#define OUT_SV_LIB_JSON "out_sv_lib" #define OUT_DFCIR_JSON "out_dfcir" #define OUT_FIRRTL_JSON "out_firrtl" @@ -50,7 +50,7 @@ #define LP_SCHEDULER_FLAG CLI_FLAG("l") #define OUTPUT_GROUP "output" #define OUT_SV_ARG CLI_ARG("out-sv") -#define OUT_SV_STUBS_ARG CLI_ARG("out-sv-stubs") +#define OUT_SV_LIB_ARG CLI_ARG("out-sv-lib") #define OUT_DFCIR_ARG CLI_ARG("out-dfcir") #define OUT_FIRRTL_ARG CLI_ARG("out-firrtl") @@ -186,9 +186,9 @@ struct HlsOptions final : public AppOptions { outputGroup->add_option(OUT_SV_ARG, outNames[OUT_FORMAT_ID_INT(SystemVerilog)], "Path to output the SystemVerilog module"); - outputGroup->add_option(OUT_SV_STUBS_ARG, - outNames[OUT_FORMAT_ID_INT(SVStubs)], - "Path to output stubs for SystemVerilog modules"); + outputGroup->add_option(OUT_SV_LIB_ARG, + outNames[OUT_FORMAT_ID_INT(SVLibrary)], + "Path to output SystemVerilog modules for generated operations"); outputGroup->add_option(OUT_DFCIR_ARG, outNames[OUT_FORMAT_ID_INT(DFCIR)], "Path to output unscheduled DFCIR"); @@ -203,7 +203,7 @@ struct HlsOptions final : public AppOptions { get(json, ASAP_SCHEDULER_JSON, asapScheduler); get(json, LP_SCHEDULER_JSON, lpScheduler); get(json, OUT_SV_JSON, outNames[OUT_FORMAT_ID_INT(SystemVerilog)]); - get(json, OUT_SV_STUBS_JSON, outNames[OUT_FORMAT_ID_INT(SVStubs)]); + get(json, OUT_SV_LIB_JSON, outNames[OUT_FORMAT_ID_INT(SVLibrary)]); get(json, OUT_DFCIR_JSON, outNames[OUT_FORMAT_ID_INT(DFCIR)]); get(json, OUT_FIRRTL_JSON, outNames[OUT_FORMAT_ID_INT(FIRRTL)]); } From 04f1acb4499a7aaadabdf653fc90069a823839e2 Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 18:12:43 +0300 Subject: [PATCH 6/8] Tests for SystemVerilog library output format were added. --- test/model/dfcxx/output_formats.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/test/model/dfcxx/output_formats.cpp b/test/model/dfcxx/output_formats.cpp index 14b61912..63c342c3 100644 --- a/test/model/dfcxx/output_formats.cpp +++ b/test/model/dfcxx/output_formats.cpp @@ -23,6 +23,14 @@ TEST(DFCxxOutputFormats, SystemVerilog) { EXPECT_EQ(kernel.compile(config, paths, dfcxx::ASAP), true); } +TEST(DFCxxOutputFormats, SystemVerilogLibrary) { + Polynomial2 kernel; + DFOutputPaths paths = { + {dfcxx::OutputFormatID::SVLibrary, NULLDEVICE} + }; + EXPECT_EQ(kernel.compile(config, paths, dfcxx::ASAP), true); +} + TEST(DFCxxOutputFormats, DFCIR) { Polynomial2 kernel; DFOutputPaths paths = { @@ -43,6 +51,7 @@ TEST(DFCxxOutputFormats, All) { Polynomial2 kernel; DFOutputPaths paths = { {dfcxx::OutputFormatID::SystemVerilog, NULLDEVICE}, + {dfcxx::OutputFormatID::SVLibrary, NULLDEVICE}, {dfcxx::OutputFormatID::DFCIR, NULLDEVICE}, {dfcxx::OutputFormatID::FIRRTL, NULLDEVICE} }; From 04059960d02932b6ee0509b429d7f621f381c6d0 Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 18:19:18 +0300 Subject: [PATCH 7/8] Minor codestyle fixes. --- src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h | 2 +- src/model/dfcir/lib/dfcir/CMakeLists.txt | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h index 05ae3163..086ab449 100644 --- a/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h +++ b/src/model/dfcir/include/dfcir/conversions/DFCIRPasses.h @@ -10,8 +10,8 @@ #define DFCIR_PASSES_H #include "dfcir/DFCIROperations.h" -#include "mlir/Pass/Pass.h" +#include "mlir/Pass/Pass.h" #include "llvm/Support/raw_ostream.h" #include "memory" diff --git a/src/model/dfcir/lib/dfcir/CMakeLists.txt b/src/model/dfcir/lib/dfcir/CMakeLists.txt index e2beb4ba..aed6ebbb 100644 --- a/src/model/dfcir/lib/dfcir/CMakeLists.txt +++ b/src/model/dfcir/lib/dfcir/CMakeLists.txt @@ -21,7 +21,10 @@ target_include_directories(MLIRDFCIR set(TEMPLATES_PATH "${PROJECT_SOURCE_DIR}/templates") -add_compile_definitions(TEMPLATES_PATH="${TEMPLATES_PATH}" STUBS_TEMPLATE_PATH="${TEMPLATES_PATH}/stubs.tpl") +add_compile_definitions( + TEMPLATES_PATH="${TEMPLATES_PATH}" + STUBS_TEMPLATE_PATH="${TEMPLATES_PATH}/stubs.tpl" +) target_link_libraries(MLIRDFCIR PUBLIC From a7237a9ea8ee582db6fb4dac9a8248108261b6cc Mon Sep 17 00:00:00 2001 From: Muxianesty Date: Thu, 8 Aug 2024 18:23:17 +0300 Subject: [PATCH 8/8] Removed empty line in stubs.tpl . --- src/model/dfcir/templates/stubs.tpl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/model/dfcir/templates/stubs.tpl b/src/model/dfcir/templates/stubs.tpl index f1ab59e0..119a393e 100644 --- a/src/model/dfcir/templates/stubs.tpl +++ b/src/model/dfcir/templates/stubs.tpl @@ -6,8 +6,7 @@ {{! Copyright 2024 ISP RAS (http://www.ispras.ru) }} {{! }} {{!===---------------------------------------------------------------------===}} -{{/LICENSE}} -// This file has been automatically generated by Utopia HLS at {{GEN_TIME}}. +{{/LICENSE}}// This file has been automatically generated by Utopia HLS at {{GEN_TIME}}. {{#FIFO_MODULES}}module {{MODULE_NAME}} (input [{{WIDTH}}:0] {{ARG1}}, output [{{WIDTH}}:0] {{RES1}}, input {{CLK}}); reg [{{WIDTH}}:0] r[{{LATENCY}}:0];