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RVB23 Profiles

Table of Contents
Warning
This document is in the development state.

Do not use for implementations. Assume everything can change.

Introduction

This document captures the current proposal for the RVB23 profile family. RVB23 is intended to be the first major release of the RVB series of RISC-V Application Processor Profile.

RVB profiles are intended to be used for customized 64-bit application processors that will run rich OS stacks, but usually as a custom build of standard OS source-code distributions. The approach is to provide a large guaranteed set of relatively inexpensive and/or widely beneficial features but allow optionality for more expensive and/or more targeted extensions.

Unlike the RVA profiles, it is explicitly a non-goal of RVB profiles to provide a single standard ISA interface supporting a wide variety of binary kernel and binary application software distributions. However, individual software ecosystems may build upon RVB profiles to produce a more targeted standard interface for a certain market.

RVB23 Profiles

Only user-mode (RVB23U64) and supervisor-mode (RVB23S64) profiles are specified in this family.

RVB23U64 Profile

The RVB23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit RVB applications processors. This is the most important profile within the application processor family in terms of the amount of software that targets this profile.

RVB23U64 Mandatory Base

RV64I is the mandatory base ISA for RVB23U64 and is little-endian. As per the unprivileged architecture specification, the ecall instruction causes a requested trap to the execution environment.

RVB23U64 Mandatory Extensions

The following mandatory extensions are also in RVA22U64.

  • M Integer multiplication and division.

  • A Atomic instructions.

  • F Single-precision floating-point instructions.

  • D Double-precision floating-point instructions.

  • C Compressed Instructions.

  • Zicsr CSR instructions. These are implied by presence of F.

  • Zicntr Base counters and timers.

  • Zihpm Hardware performance counters.

  • Ziccif Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVB23) are atomic.

  • Ziccrse Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.

  • Ziccamoa Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic.

  • Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.

  • Za64rs Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes.

  • Zihintpause Pause instruction.

  • Zba Address computation.

  • Zbb Basic bit manipulation.

  • Zbs Single-bit instructions.

  • Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.

  • Zicbom Cache-Block Management Operations.

  • Zicbop Cache-Block Prefetch Operations.

  • Zicboz Cache-Block Zero Operations.

  • Zkt Data-independent execution time.

The following mandatory extensions are also present in RVA23U64:

  • Zihintntl Non-temporal locality hints.

  • Zicond Conditional Zeroing instructions.

  • Zimop Maybe Operations.

  • Zcmop Compressed Maybe Operations.

  • Zcb Additional 16b compressed instructions.

  • Zfa Additional scalar FP instructions.

  • Zawrs Wait on reservation set.

RVB23U64 Optional Extensions

RVB23U64 has 18 profile options listed below.

Localized Options

The following extensions are localized options in both RVA23U64 and RVB23U64:

  • Zvbc Vector carryless multiply.

  • Zvkng Vector Crypto NIST Algorithms including GHASH.

  • Zvksg Vector Crypto ShangMi Algorithms including GHASH.

The following extensions options are localized options in RVB23U64 but are not present in RVA23U64:

  • Zvkg Vector GHASH instructions

  • Zvknc Vector Crypto NIST Algorithms with carryless multiply

  • Zvksc Vector Crypto ShangMi Algorithms with carryless multiply

Note
 RVA profiles mandate the higher-performing but more expensive GHASH options when adding vector crypto. To reduce implementation cost, RVB profiles also allow these carryless multiply options (Zvknc and Zvksc) to implement GCM efficiently, with GHASH available as a separate option.

  • Zkn Scalar Crypto NIST Algorithms.

  • Zks Scalar Crypto ShangMi Algorithms.

Note
 RVA23 profiles drop support for scalar crypto as an option, as the vector extension is now mandatory in RVA23. RVB23 profiles support scalar crypto, as the vector extension is optional in RVB23.
Development Options

The following are new development options intended to become mandatory in RVB24U64:

  • Zabha Byte and Halfword Atomic Memory Operations

  • Zacas Compare-and-swap

  • Ziccamoc Main memory regions with both the cacheability and coherence PMAs must provide AMOCASQ level PMA support.

  • Zama16b Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.

Expansion Options

The following extensions are mandatory in RVA23U64 but are expansion options in RVB23U64:

  • Zfhmin Half-Precision Floating-point transfer and convert.

  • V Vector Extension.

Note
 Unclear if other Zve* extensions should also be supported in RVB.

  • Zvfhmin Vector FP16 conversion instructions.

  • Zvbb Vector bitmanip extension.

  • Zvkt Vector data-independent execution time.

  • Supm Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

The following extensions are expansion options in both RVA23U64 and RVB23U64:

  • Zfh Scalar Half-Precision Floating-Point (FP16).

  • Zbc Scalar carryless multiply.

  • Zvfh Vector half-precision floating-point (FP16).

  • Zfbfmin Scalar BF16 FP conversions.

  • Zvfbfmin Vector BF16 FP conversions.

  • Zvfbfwma Vector BF16 widening mul-add.

The following are RVA23U64 development options as they are intended to become mandatory in RVA24U64 profile, but are considered expansion options for RVB23U64 as they are not intended to be made mandatory in RVB profiles:

  • Zvbc Vector carryless multiply.

Transitory Options

There are no transitory options in RVB23U64.

RVB23U64 Recommendations

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

RVB23S64 Profile

The RVB23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVB23S64 is based on privileged architecture version 1.13.

Note
 Priv 1.13 is still being defined.

RVB23S64 Mandatory Base

RV64I is the mandatory base ISA for RVB23S64 and is little-endian. The ecall instruction operates as per the unprivileged architecture specification. An ecall in user mode causes a contained trap to supervisor mode. An ecall in supervisor mode causes a requested trap to the execution environment.

RVB23S64 Mandatory Extensions

The following unprivileged extensions are mandatory:

  • The RVB23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVB23U64.

  • Zifencei Instruction-Fetch Fence.

Note
 Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVB23 application processors. A new instruction-cache coherence mechanism is under development (tentatively named Zjid) which might be added as an option in the future.

The following privileged extensions are mandatory, and are also mandatory in RVA23S64.

  • Ss1p13 Supervisor Architecture version 1.13.

Note
 Ss1p13 supersedes Ss1p12 but is not yet ratified.

  • Svnapot NAPOT Translation Contiguity

Note
 Svnapot is very low cost to provide, so is made mandatory even in RVB.

  • Svbare The satp mode Bare must be supported.

  • Sv39 Page-Based 39-bit Virtual-Memory System.

  • Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.

  • Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.

  • Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.

  • Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions. For illegal-instruction exceptions, stval must be written with the faulting instruction.

  • Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.

  • Svpbmt Page-Based Memory Types

  • Svinval Fine-Grained Address-Translation Cache Invalidation

  • Sstc supervisor-mode timer interrupts.

  • Sscofpmf Count Overflow and Mode-Based Filtering.

  • Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).

RVB23S64 Optional Extensions

RVB23S64 has the same unprivileged options as RVB23U64,

RVB23S64 has the same six privileged options (Sv48, Sv57, Svadu, Sscofpmf, Zkr, H) as RVA23S64.

Localized Options

There are no privileged localized options in RVB23S64.

Development Options

There are no privileged development options in RVB23S64.

Expansion Options

The following privileged expansion options are mandatory in RVA22S64 but options in RVB23S64:

  • Ssnpm Pointer masking, with senvcfg.PME supporting at minimum, settings PMLEN=0 and PMLEN=7.

  • Sspm Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

The following hypervisor extension and mandates were also in RVA22S64 and are available as an expansion option in RVB23S64:

  • H The hypervisor extension.

When the hypervisor extension is implemented, the following are also mandatory:

  • Ssstateen Supervisor-mode view of the state-enable extension. The supervisor-mode (sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers must be provided.

  • Shcounterenw For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable.

  • Shvstvala vstval must be written in all cases described above for stval.

  • Shtvala htval must be written with the faulting guest physical address in all circumstances permitted by the ISA.

  • Shvstvecd vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address.

  • Shvsatpa All translation modes supported in satp must be supported in vsatp.

  • Shgatpa For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported.

  • If the hypervisor extension is implemented and pointer masking (Ssnpm) is supported then henvcfg.PME must support at minimum, settings PMLEN=0 and PMLEN=7.

The following privileged expansion options are also present in RVA23S64:

  • Sv48 Page-Based 48-bit Virtual-Memory System.

  • Sv57 Page-Based 57-bit Virtual-Memory System.

  • Svadu Hardware A/D bit updates.

  • Zkr Entropy CSR.

  • Svadu Hardware A/D bit updates.

  • Sdext Debug triggers

  • Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.

Note
 Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs.

  • Svvptc Transitions from invalid to valid PTEs will be visible in bounded time without an explicit SFENCE.

RVB23S64 Recommendations

  • Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes.

Glossary of ISA Extensions

The following unprivileged ISA extensions are defined in Volume I of the RISC-V Instruction Set Manual.

  • M Extension for Integer Multiplication and Division

  • A Extension for Atomic Memory Operations

  • F Extension for Single-Precision Floating-Point

  • D Extension for Double-Precision Floating-Point

  • Q Extension for Quad-Precision Floating-Point

  • C Extension for Compressed Instructions

  • Zifencei Instruction-Fetch Synchronization Extension

  • Zicsr Extension for Control and Status Register Access

  • Zicntr Extension for Basic Performance Counters

  • Zihpm Extension for Hardware Performance Counters

  • Zihintpause Pause Hint Extension

  • Zfh Extension for Half-Precision Floating-Point

  • Zfhmin Minimal Extension for Half-Precision Floating-Point

  • Zfinx Extension for Single-Precision Floating-Point in x-registers

  • Zdinx Extension for Double-Precision Floating-Point in x-registers

  • Zhinx Extension for Half-Precision Floating-Point in x-registers

  • Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers

The following privileged ISA extensions are defined in Volume II of the RISC-V Instruction Set Manual.

  • Sv32 Page-based Virtual Memory Extension, 32-bit

  • Sv39 Page-based Virtual Memory Extension, 39-bit

  • Sv48 Page-based Virtual Memory Extension, 48-bit

  • Sv57 Page-based Virtual Memory Extension, 57-bit

  • Svpbmt, Page-Based Memory Types

  • Svnapot, NAPOT Translation Contiguity

  • Svinval, Fine-Grained Address-Translation Cache Invalidation

  • Hypervisor Extension

  • Sm1p11, Machine Architecture v1.11

  • Sm1p12, Machine Architecture v1.12

  • Ss1p11, Supervisor Architecture v1.11

  • Ss1p12, Supervisor Architecture v1.12

  • Ss1p13, Supervisor Architecture v1.13

The following extensions have not yet been incorporated into the RISC-V Instruction Set Manual; the hyperlinks lead to their separate specifications.