publications.bib

@inproceedings{aortcc,
    keywords     = {talks},
    title        = {Development and Evaluation of the Eclipse OMR Library on AArch64 using the Eclipse OpenJ9 Runtime},
    author       = {\uline{J.-P. Legault} and A.G. Graham and H. Soontiens and M. Flawn and Md.M. Rahman and K.B. Kent and D. Maier and K. Konno},
    date         = {2019-11-05},
    organization = {IBM Corp.},
    location     = {Markham, Ontario, Canada},
    eventtitle   = {3rd Workshop on Advances in Open Runtime Technology for Cloud Computing (AORTCC 2019}
}

@inproceedings{aorcpt,
    keywords     = {talks},
    title        = {Evaluation of Eclipse OpenJ9 on AArch64},
    author       = {\uline{J.-P. Legault} and A.G. Graham and K.B. Kent and D. Maier and K. Konno},
    date         = {2020-11-13},
    organization = {IBM Corp.},
    location     = {Markham, Ontario, Canada},
    eventtitle   = {4th Workshop on Advances in Open Runtime and Cloud Performance Technology (AORCPT 2020}
}

@inproceedings{batch,
    keywords  = {poster},
    author    = {\uline{M. Patrou} and J. Legault and A. G. Graham and K. B. Kent},
    booktitle = {2019 22nd Euromicro Conference on Digital System Design (DSD)},
    title     = {Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation},
    location  = {Chalkidiki, Greece, Greece},
    publisher = {IEEE Xplore},
    pages     = {144-151},
    abstract  = {Integrated circuit simulators reproduce the behavior and functionality of the underlying circuits. They are part of FPGA CAD flow tools and they ensure the correctness of the circuits after the various conversions and optimizations occurring in the previous stages. During this procedure a graph with dependencies across nodes is created for each circuit design. Large circuits, and thus graphs, require more time to be simulated, making a parallel approach necessary. We explore a new solution-batch-parallel simulation in which the circuit output is calculated by worker threads that process batches of input vectors. The threads traverse and calculate their assigned nodes in parallel taking into consideration the intra-node dependencies. Furthermore, a node calculation analysis is performed and used to achieve work balance across threads. We apply this technique on the open-source Odin II framework and compare it with the existing approaches. The batch-parallel simulation is compared with the two existing approaches, single-threaded and multi-threaded, under various configurations, considering the number of threads and the batch sizes. The results demonstrate performance gains against the existing approaches in the majority of the benchmarks used for specific metrics, such as simulation elapsed time.},
    doi       = {10.1109/DSD.2019.00031},
    date      = {2019-08-01},
    keywords  = {publishedpapers}
}
  

@inproceedings{castle,
    keywords     = {poster},
    title        = {Language Runtimes on Embedded Architectures},
    author       = {\uline{J.-P. Legault} and \uline{A. Graham} and Dr. K.B. Kent and D. Maier and J. Kingdon},
    date         = {2018-05-08},
    organization = {IBM Canada Lab},
    location     = {Markham, Ontario, Canada},
    eventtitle   = {CASTLE 2018}
}


@inproceedings{castle20,
    keywords     = {poster},
    title        = {AArch64 Support for the Eclipse OMR Language Runtime Toolkit \& Eclipse OpenJ9},
    author       = {\uline{Md.A. Noor} and J.-P. Legault and Md.A. Haque and S.S. Ponangi and A.G. Graham and K.B. Kent and G.W. Dueck and D. Maier},
    date         = {2020-05-11},
    organization = {IEEE Xplore},
    location     = {Markham, Ontario, Canada},
    eventtitle   = {CASTLE 2020}
}

@inproceedings{evoke_poster,
    keywords     = {poster},
    title        = {Building AArch64 Support for Eclipse OpenJ9 and Eclipse OMR},
    author       = {\uline{A.G. Graham} and J.-P. Legault and H. Soontiens and M. Flawn and Md.M. Rahman and K.B. Kent and D. Maier and K. Konno},
    date         = {2019-11-05},
    organization = {IBM Corp.},
    location     = {Markham, Ontario, Canada},
    eventtitle   = {29th Annual International Conference on Computer Science and Software Engineering (CASCON x EVOKE 2019)}
}
  

@onlne{google,
    title        = {Google awards UNB researcher funding for FPGAs},
    author       = {UNB Newsroom},
    date         = {2020-09-15},
    organization = {University of New Brunswick},
    url          = {https://blogs.unb.ca/newsroom/2020/09/google-awards-unb-researcher-funding-for-fpgas.php},
}

@inproceedings{hbmul,
    keywords     = {publishedpapers},
    title        = {Hard and Soft Logic Trade-offs for Multipliers in VTR.},
    author       = {\uline{G. Krylov} and J.P. Legault and K.B. Kent},
    date         = {2020-08-26},
    organization = {IEEE Xplore},
    location     = {Portorož, Slovenia},
    eventtitle   = {Euromicro DSD/SEAA 2020}
}

@inproceedings{honours,
    keywords     = {dissertations},
    title        = {Experimental verilog synthesis features for Odin II and alternative multiplier hard-block for fpga},
    author       = {\uline{J.-P. Legault}},
    date         = {2018-09-01},
    organization = {University of New Brunswick},
    location     = {Fredericton, New Brunwick, Canada},
    eventtitle   = {Honours Thesis defended at the University of New Brunswick}
}

@inproceedings{honours.talk,
    keywords     = {talks},
    title        = {Experimental verilog synthesis features for Odin II and alternative multiplier hard-block for fpga},
    author       = {\uline{J.-P. Legault}},
    date         = {2018-10-01},
    organization = {University of New Brunswick},
    location     = {Fredericton, New Brunwick, Canada},
    eventtitle   = {12th Annual Conference for Science Atlantic Mathematics, Statistics and Computer Science by the Atlantic Association for Research in the Mathematical Sciences (AARMS)}
}

@inproceedings{loop,
    keywords  = {publishedpapers},
    author    = {\uline{Young, Scott} and Demmings, Alexandrea and Ivari, Nasrin Eshraghi and Legault, Jean-Philippe and Kent, Kenneth B.},
    title     = {Verilog Loop Unrolling, Module Generation, Part-Select and Arithmetic Right Shift Support in Odin II},
    date      = {2019-10-17},
    publisher = {Association for Computing Machinery},
    address   = {New York, NY, USA},
    booktitle = {Proceedings of the 30th International Workshop on Rapid System Prototyping (RSP’19)},
    location  = {New York, NY, USA}
}

@inproceedings{odin11beyond,
    keywords     = {poster},
    title        = {Improved Synthesis and Simulation for FPGAs: ODIN II for VTR 8.0 and Beyond},
    author       = {\uline{A.G. Graham} and J.-P. Legault and M. Patrou and K.B. Kent},
    date         = {2019-04-12},
    organization = {University of New Brunswick},
    location     = {Fredericton, New Brunswick, Canada},
    eventtitle   = {16th Annual Research Exposition of the UNB Faculty of Computer Science}
}

@inproceedings{omr.cascon.18,
    keywords     = {talks},
    title        = {AArch64 Support for the OMR Language Runtime Toolkit},
    author       = {\uline{J.-P. Legault} and A. Graham and Dr. K.B. Kent and D. Maier and K. Konno},
    date         = {2018-10-29},
    organization = {IBM Corp.},
    location     = {Markham, Ontario, Canada },
    eventtitle   = {2nd Annual Workshop on Advances in Open Runtime Technology for Cloud Environments, CASCON 2018}
}

@inproceedings{omr.cascon.poster.18,
    keywords     = {poster},
    title        = {AArch64 Support for the OMR Language Runtime Toolkit},
    author       = {\uline{J.-P. Legault} and \uline{A. Graham} and Dr. K.B. Kent and D. Maier and K. Konno},
    date         = {2018-10-29},
    organization = {IBM Corp.},
    location     = {Markham, Ontario, Canada},
    eventtitle   = {2nd Annual Workshop on Advances in Open Runtime Technology for Cloud Environments, CASCON 2018}
}

@inproceedings{omr.turbo.18,
    keywords     = {talks},
    title        = {AArch64 Support for the OMR Language Runtime Toolkit},
    author       = {\uline{J.-P. Legault} and A. Graham and Dr. K.B. Kent and D. Maier and K. Konno},
    date         = {2018-11-04},
    organization = {IBM Corp.},
    location     = {Boston, United States},
    eventtitle   = {TURBO’18 Building Language Runtimes with Eclipse OMR Workshop, SPLASH 2018}
}

@inproceedings{texpo,
    keywords     = {poster},
    title        = {Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA},
    author       = {\uline{J.-P. Legault} and P. Patros and Dr. K.B. Kent},
    date         = {2018-10-23},
    organization = {CMC},
    location     = {Toronto, Ontario, Canada},
    eventtitle   = {Innovation 360, Texpo 2018}
}

@inproceedings{trainable,
    keywords  = {publishedpapers},
    author    = {J.-P. Legault and P. Patros and \uline{K. B. Kent}},
    booktitle = {2018 International Symposium on Rapid System Prototyping (RSP)},
    title     = {Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA},
    publisher = {IEEE Xplore},
    pages     = {90-96},
    date      = {2018-10-04},
    location  = {Torino, Italy}
}

@inproceedings{trainable_ml,
    keywords  = {publishedpapers},
    author    = {\uline{S.A. Damghani} and J.-P. Legault and K.B. Kent},
    booktitle = {2020 International Symposium on Rapid System Prototyping (RSP)},
    title     = {Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin II},
    publisher = {IEEE Xplore},
    date      = {2020-09-01},
    location  = {Undef},
    pages     = {Undef}
}

@inproceedings{unb,
    keywords     = {poster},
    title        = {Language Runtimes on Embedded Architectures},
    author       = {\uline{J.-P. Legault} and \uline{A. Graham} and Dr. K.B. Kent and D. Maier and J. Kingdon},
    date         = {2018-04-11},
    organization = {University of New Brunswick},
    location     = {Fredericton, New Brunswick, Canada},
    eventtitle   = {15th Annual Research Exposition of the UNB Faculty of Computer Science}
}

@inproceedings{vtr8,
    keywords  = {publishedpapers},
    author    = {Murray, Kevin E. and Petelin, Oleg and Zhong, Sheng and Wang, Jia Min and Eldafrawy, Mohamed and Legault, Jean-Philippe and Sha, Eugene and Graham, Aaron G. and Wu, Jean and Walker, Matthew J. P. and Zeng, Hanqing and Patros, Panagiotis and Luu, Jason and Kent, Kenneth B. and Betz, Vaughn},
    title     = {VTR 8: High-Performance CAD and Customizable FPGA Architecture Modelling},
    publisher = {Association for Computing Machinery},
    address   = {New York, NY, USA},
    journal   = {ACM Trans. Reconfigurable Technol. Syst.},
    date      = {2020-06-01}
}

@inproceedings{xdocker_poster,
    keywords     = {poster},
    title        = {XDocker: A Cross-Platform Tool for ​Continuous Development},
    author       = {\uline{J.-P. Legault} and Aaron G. Graham and Kenneth B. Kent and D. Maier},
    date         = {2019-11-05},
    organization = {IBM Corp.},
    location     = {Markham, Ontario, Canada},
    eventtitle   = {29th Annual International Conference on Computer Science and Software Engineering (CASCON x EVOKE 2019)}
}