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sim6809.c
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/* M6800 Simulator
* Copyright
* (C) 2011 Joseph H. Allen
*
* This is free software; you can redistribute it and/or modify it under the
* terms of the GNU General Public License as published by the Free Software
* Foundation; either version 1, or (at your option) any later version.
*
* It is distributed in the hope that it will be useful, but WITHOUT ANY
* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License along with
* this software; see the file COPYING. If not, write to the Free Software Foundation,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "exor.h"
#include "unasm6800.h"
#include "asm6800.h"
#include "sim6800.h"
int skip = 0; /* Skip first nn instructions in trace */
int trace = 0; /* Enable instruction trace */
int stop; /* Stop flag */
int reset; /* User hit reset */
int abrt; /* User hit abort */
int sp_stop;
/* Breakpoint */
int mybrk;
unsigned short brk_addr;
/* CPU registers */
unsigned char acca;
unsigned char accb;
unsigned short ix;
unsigned short iy;
unsigned short up;
unsigned short sp;
unsigned short pc;
unsigned char dp;
unsigned char c_flag;
unsigned char v_flag;
unsigned char z_flag;
unsigned char n_flag;
unsigned char i_flag; /* 1=masked, 0=enabled */
unsigned char h_flag;
unsigned char f_flag; /* FIRQ mask */
unsigned char e_flag; /* All registers saved if set */
unsigned char read_flags()
{
return (c_flag + (v_flag << 1) + (z_flag << 2) + (n_flag << 3) + (i_flag << 4) + (h_flag << 5) + (f_flag << 6) + (e_flag << 7));
}
void write_ireg(int r, unsigned short data)
{
switch (r)
{
case 0: ix = data; break;
case 1: iy = data; break;
case 2: up = data; break;
case 3: sp = data; break;
}
}
unsigned short ireg(int r)
{
unsigned short regs[4];
regs[0] = ix;
regs[1] = iy;
regs[2] = up;
regs[3] = sp;
return regs[r];
}
void write_flags(unsigned char f)
{
c_flag = (f & 1);
v_flag = ((f >> 1) & 1);
z_flag = ((f >> 2) & 1);
n_flag = ((f >> 3) & 1);
i_flag = ((f >> 4) & 1);
h_flag = ((f >> 5) & 1);
f_flag = ((f >> 6) & 1);
e_flag = ((f >> 7) & 1);
}
/* Trace buffer */
int trace_idx;
#define TRACESIZE 128
/* Machine state before this instruction */
struct trace_entry
{
unsigned char acca;
unsigned char accb;
unsigned short ix;
unsigned short iy;
unsigned short up;
unsigned short sp;
unsigned short pc; /* Address of instruction */
unsigned char dp;
unsigned char cc;
unsigned short ea; /* Effective address */
unsigned short data; /* Data read or written to effective address */
unsigned char insn[5]; /* Copy of instruction */
unsigned short status; /* Bit 0 set: instruction completed normally. Bit 1 set: subroutine handled by simulator */
} trace_buf[TRACESIZE];
void record_trace(struct trace_entry *t)
{
t->acca = acca;
t->accb = accb;
t->ix = ix;
t->iy = iy;
t->up = up;
t->sp = sp;
t->pc = pc;
t->dp = dp;
t->cc = read_flags();
t->insn[0] = mread(pc);
t->insn[1] = mread(pc + 1);
t->insn[2] = mread(pc + 2);
t->insn[3] = mread(pc + 3);
t->insn[4] = mread(pc + 4);
t->ea = 0;
t->data = 0;
t->status = 0;
}
unsigned short mread2(unsigned short addr)
{
return (mread(addr) << 8) + mread(addr + 1);
}
/* Fetch instruction byte, record copy in trace entry */
unsigned char fetch()
{
unsigned char c = mread(pc++);
return c;
}
unsigned short fetch2()
{
unsigned short v;
v = fetch();
v = (v << 8) + fetch();
return v;
}
void mwrite2(unsigned short addr, unsigned short data)
{
mwrite(addr, (data >> 8));
mwrite(addr + 1, (data & 0xFF));
}
void pushs(unsigned char data)
{
mwrite(--sp, data);
}
void pushu(unsigned char data)
{
mwrite(--up, data);
}
unsigned char pull()
{
return mread(sp++);
}
unsigned char pullu()
{
return mread(up++);
}
void pushs2(unsigned short data)
{
pushs(data & 0xFF);
pushs(data >> 8);
}
unsigned short pull2()
{
unsigned short w;
w = pull();
w = (w << 8) + pull();
return w;
}
void pushu2(unsigned short data)
{
pushu(data & 0xFF);
pushu(data >> 8);
}
unsigned short pullu2()
{
unsigned short w;
w = pullu();
w = (w << 8) + pullu();
return w;
}
/* TFR get/put */
int tfr_get(unsigned short *rtn, int r)
{
switch (r) {
case 0x0: *rtn = accd; return 0;
case 0x1: *rtn = ix; return 0;
case 0x2: *rtn = iy; return 0;
case 0x3: *rtn = up; return 0;
case 0x4: *rtn = sp; return 0;
case 0x5: *rtn = pc; return 0;
case 0x8: *rtn = acca; return 0;
case 0x9: *rtn = accb; return 0;
case 0xA: *rtn = read_flags(); return 0;
case 0xB: *rtn = dp; return 0;
}
return -1;
}
int tfr_put(int r, unsigned short val)
{
switch (r) {
case 0x0: acca = (val >> 8); accb = val; return 0;
case 0x1: ix = val; return 0;
case 0x2: iy = val; return 0;
case 0x3: up = val; return 0;
case 0x4: sp = val; return 0;
case 0x5: jump(val); return 0;
case 0x8: acca = val; return 0;
case 0x9: accb = val; return 0;
case 0xA: write_flags(val); return 0;
case 0xB: dp = val; return 0;
}
return -1;
}
int tfr_name(char **name, int r)
{
switch (r) {
case 0x0: *name = "D"; return 0;
case 0x1: *name = "X"; return 0;
case 0x2: *name = "Y"; return 0;
case 0x3: *name = "U"; return 0;
case 0x4: *name = "S"; return 0;
case 0x5: *name = "PC"; return 0;
case 0x8: *name = "A"; return 0;
case 0x9: *name = "B"; return 0;
case 0xA: *name = "CC"; return 0;
case 0xB: *name = "DP"; return 0;
}
return -1;
}
/* Push all registers */
void push_all()
{
e_flag = 1; /* Set e_flag so that RTI knows to restore all regs */
pushs2(pc);
pushs2(up);
pushs2(iy);
pushs2(ix);
pushs(dp);
pushs2(accd);
pushs(read_flags());
}
/* Process indexed mode post byte, return effective address */
int ind(unsigned short *rtn)
{
unsigned char i = fetch(); /* Fetch index byte */
unsigned char ind = (i & 0x10); /* Indirection bit */
unsigned char o = (i & 0x0f); /* Index type / low bits of 5-bit offset */
int r = (3 & (i >> 5)); /* Index register number */
unsigned short ea;
if (!(i & 0x80))
{ /* 5-bit signed offset */
ea = ireg(r);
if (ind) {
*rtn = ea + o + 0xFFF0;
return 0;
} else {
*rtn = ea + o;
return 0;
}
}
else
{
switch (o)
{
case 0x00: /* ,R+ */
{
ea = ireg(r);
write_ireg(r, ea + 1);
if (ind) /* Not valid!? */
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x01: /* ,R++ */
{
ea = ireg(r);
write_ireg(r, ea + 2);
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x02: /* ,-R */
{
ea = ireg(r) - 1;
write_ireg(r, ea);
if (ind) /* Not valid!? */
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x03: /* ,--R */
{
ea = ireg(r) - 2;
write_ireg(r, ea);
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x04: /* ,R */
{
ea = ireg(r);
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x05: /* B,R */
{
ea = ireg(r);
ea += (signed char)accb;
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x06: /* A,R */
{
ea = ireg(r);
ea += (signed char)acca;
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x08: /* Offset8,R */
{
ea = ireg(r);
ea += (signed char)fetch();
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x09: /* Offset16,R */
{
ea = ireg(r);
ea += fetch2();
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x0B: /* D,R */
{
ea = ireg(r) + accd;
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x0C: /* Offset8,PC */
{
unsigned char o = fetch();
ea = pc + (signed char)o;
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x0D: /* Offset16,PC */
{
unsigned short o = fetch2();
ea = pc + o;
if (ind)
ea = mread2(ea);
*rtn = ea;
return 0;
}
case 0x0F: /* Offset16 */
{
unsigned short ea = fetch2();
if (ind) /* Must be true here? */
ea = mread2(ea);
*rtn = ea;
return 0;
}
}
}
/* Unknown if we get here... */
return -1;
}
/* Show indexed */
char *regname[]=
{
"X", "Y", "U", "S"
};
int show_ind(struct trace_entry *t, int *x, char *buf, char *right)
{
unsigned char i = t->insn[*x]; /* Fetch index byte */
unsigned char ind = (i & 0x10); /* Indirection bit */
unsigned char o = (i & 0x0f); /* Index type / low bits of 5-bit offset */
int r = (3 & (i >> 5)); /* Index register number */
sprintf(buf + strlen(buf), " %2.2X", i);
*x = *x + 1;
if (!(i & 0x80))
{ /* 5-bit signed offset */
if (ind) {
int v = -16 + o;
sprintf(right, "%d,%s", v, regname[r]);
return 0;
} else {
sprintf(right, "%d,%s", o, regname[r]);
return 0;
}
}
else
{
switch (o)
{
case 0x00: /* ,R+ */
{
if (ind)
sprintf(right, "[,%s+]", regname[r]);
else
sprintf(right, ",%s+", regname[r]);
return 0;
}
case 0x01: /* ,R++ */
{
if (ind)
sprintf(right, "[,%s+]+", regname[r]);
else
sprintf(right, ",%s++", regname[r]);
return 0;
}
case 0x02: /* ,-R */
{
if (ind)
sprintf(right, "[,-%s]", regname[r]);
else
sprintf(right, ",-%s", regname[r]);
return 0;
}
case 0x03: /* ,--R */
{
if (ind)
sprintf(right, "[,--%s]", regname[r]);
else
sprintf(right, ",--%s", regname[r]);
return 0;
}
case 0x04: /* ,R */
{
if (ind)
sprintf(right, "[,%s]", regname[r]);
else
sprintf(right, ",%s", regname[r]);
return 0;
}
case 0x05: /* B,R */
{
if (ind)
sprintf(right, "[B,%s]", regname[r]);
else
sprintf(right, "B,%s", regname[r]);
return 0;
}
case 0x06: /* A,R */
{
if (ind)
sprintf(right, "[A,%s]", regname[r]);
else
sprintf(right, "A,%s", regname[r]);
return 0;
}
case 0x08: /* Offset8,R */
{
unsigned short v = (signed char)t->insn[*x];
sprintf(buf + strlen(buf), " %2.2X", t->insn[*x]);
*x = *x + 1;
if (ind)
sprintf(right, "[%d,%s]", (signed short)v, regname[r]);
else
sprintf(right, "%d,%s", (signed short)v, regname[r]);
return 0;
}
case 0x09: /* Offset16,R */
{
unsigned short v = (t->insn[*x] << 8);
sprintf(buf + strlen(buf), " %2.2X", t->insn[*x]);
*x = *x + 1;
v += t->insn[*x];
sprintf(buf + strlen(buf), "%2.2X", t->insn[*x]);
*x = *x + 1;
if (ind)
sprintf(right, "[%d,%s]", (signed short)v, regname[r]);
else
sprintf(right, "%d,%s", (signed short)v, regname[r]);
return 0;
}
case 0x0B: /* D,R */
{
if (ind)
sprintf(right, "[D,%s]", regname[r]);
else
sprintf(right, "D,%s", regname[r]);
return 0;
}
case 0x0C: /* Offset8,PC */
{
unsigned short v = (signed char)t->insn[*x];
sprintf(buf + strlen(buf), " %2.2X", t->insn[*x]);
*x = *x + 1;
if (ind)
sprintf(right, "[$%x,PCR]", (unsigned short)(t->pc + *x + v));
else
sprintf(right, "$%x,PCR", (unsigned short)(t->pc + *x + v));
return 0;
}
case 0x0D: /* Offset16,PC */
{
unsigned short v = (t->insn[*x] << 8);
sprintf(buf + strlen(buf), " %2.2X", t->insn[*x]);
*x = *x + 1;
v += t->insn[*x];
sprintf(buf + strlen(buf), "%2.2X", t->insn[*x]);
*x = *x + 1;
if (ind)
sprintf(right, "[$%x,PCR]", (unsigned short)(t->pc + *x + v));
else
sprintf(right, "$%x,PCR", (unsigned short)(t->pc + *x + v));
return 0;
}
case 0x0F: /* Offset16 */
{
unsigned short v = (t->insn[*x] << 8);
sprintf(buf + strlen(buf), " %2.2X", t->insn[*x]);
*x = *x + 1;
v += t->insn[*x];
sprintf(buf + strlen(buf), "%2.2X", t->insn[*x]);
*x = *x + 1;
if (ind)
sprintf(right, "[$%4.4x]", v);
else
sprintf(right, "$%4.4x", v);
return 0;
}
}
}
/* Unknown if we get here... */
return -1;
}
/* Show register list */
void show_list(int us, char *right, unsigned char cb)
{
int first = 0;
if (cb & 0x80) { strcat(right, first ? ",PC" : "PC"); first = 1; }
if (cb & 0x40) {
if (us)
{ strcat(right, first ? ",S" : "S"); first = 1; }
else
{ strcat(right, first ? ",U" : "U"); first = 1; }
}
if (cb & 0x20) { strcat(right, first ? ",Y" : "Y"); first = 1; }
if (cb & 0x10) { strcat(right, first ? ",X" : "X"); first = 1; }
if (cb & 0x08) { strcat(right, first ? ",DP" : "DP"); first = 1; }
if (cb & 0x04) { strcat(right, first ? ",B" : "B"); first = 1; }
if (cb & 0x02) { strcat(right, first ? ",A" : "A"); first = 1; }
if (cb & 0x01) { strcat(right, first ? ",CC" : "CC"); first = 1; }
}
#define IMM() (fetch(), (pc - 1))
#define IMM2() (fetch2(), (pc - 2))
#define DIR() ((dp << 8) + fetch())
#define EXT() (fetch2())
/* Macros which update flags following an arithmetic or logical operation */
#define Z_16(n) ((~((n) | -(n)) >> 15) & 1)
#define Z(n) (( ~((n) | -(n)) >> 7) & 1)
#define N_16(n) ((n >> 15) & 1)
#define N(n) ((n >> 7) & 1)
#define V_16(a,b,f) (((((f) ^ (a)) & ((f) ^ (b))) >> 15) & 1)
#define V(a,b,f) (((((f) ^ (a)) & ((f) ^ (b))) >> 7) & 1)
#define V_16_SUB(a,b,f) (((((a) ^ (b)) & ((f) ^ (a))) >> 15) & 1)
#define V_SUB(a,b,f) (((((a) ^ (b)) & ((f) ^ (a))) >> 7) & 1)
#define C_16(a,b,f) (((((a) & (b)) | (((a) | (b)) & ~(f))) >> 15) & 1)
#define C(a,b,f) (((((a) & (b)) | (((a) | (b)) & ~(f))) >> 7) & 1)
#define C_16_SUB(a,b,f) ((((~(a) & (b)) | ((~(a) | (b)) & (f))) >> 15) & 1)
#define C_SUB(a,b,f) ((((~(a) & (b)) | ((~(a) | (b)) & (f))) >> 7) & 1)
#define H(a,b,f) ((((f) ^ (a) ^ (b)) >> 4) & 1)
/* Print one trace line */
void show_trace(int insn_no, struct trace_entry *t)
{
int x;
char *fact_label;
char *fact_comment;
char *ea_label;
char buf_ea[80];
char buf1[80];
char buf[80]; /* Address and fetched data */
char right[20]; /* Address mode / operand */
char buf3[120]; /* Effective address and data */
char *insn = "Huh?";
char *left = ""; /* Left operand, like the 'D' in ADDD */
int subr = 0;
right[0] = 0;
buf3[0] = 0;
buf[0] = 0;
/* Any facts about this address? */
fact_label = find_label(t->pc);
fact_comment = "";
if (!fact_label) {
if (facts[t->pc]) {
fact_label = facts[t->pc]->label;
fact_comment = facts[t->pc]->comment;
} else {
fact_label = "";
}
}
/* About the effective address? */
ea_label = find_label(t->ea);
if (!ea_label && facts[t->ea])
ea_label = facts[t->ea]->label;
if (ea_label)
sprintf(buf_ea, "(%s)", ea_label);
else
buf_ea[0] = 0;
if (t->status == 2) {
if (insn_no >= skip) {
fprintf(mon_out, " %10d ---- Subroutine at %4.4X processed by simulator ---- RTS executed ---\n\n",
insn_no, t->pc);
return;
}
}
/* PC */
x = 0;
sprintf(buf,"%4.4X: %2.2X", t->pc, t->insn[x]);
/* Decode instruction: */
/* Set 'insn' to instruction mnemonic */
/* Set operand to its operand */
/* Fetch op-code, deal with page2/page3 */
unsigned char opcode = t->insn[x++];
int page2 = 0;
int page3 = 0;
if (opcode == 0x10) {
page2 = 1;
sprintf(buf + strlen(buf), "%2.2X", t->insn[x]);
opcode = t->insn[x++];
} else if (opcode == 0x11) {
page3 = 1;
sprintf(buf + strlen(buf), "%2.2X", t->insn[x]);
opcode = t->insn[x++];
}
if (opcode & 0x80) { /* R,M operations */
unsigned char lowop = (opcode & 0x0F);
int sixteen = 0; /* Assume 8-bit */
int memop = 0;
/* Get operand A */
if (opcode & 0x40) {
if (lowop == 0x3 || lowop == 0xC || lowop == 0xD) {
left = "D";
sixteen = 1;
} else if (lowop == 0xE || lowop == 0xF) {
sixteen = 1;
if (page2) {
left = "S";
} else {
left = "U";
}
} else {
left = "B";
}
} else {
if (lowop == 0x3) {
sixteen = 1;
if (page3) {
left = "U";
} else {
left = "D";
}
} else if (lowop == 0xC) {
sixteen = 1;
if (page2) {
left = "Y";
} else if (page3) {
left = "S";
} else {
left = "X";
}
} else if (lowop == 0x0E || lowop == 0x0F) {
sixteen = 1;
if (page2) {
left = "Y";
} else {
left = "X";
}
} else {
/* will get here for lowop == 0x0D, but it's OK */
left = "A";
}
}
/* Get operand B's effective address */
switch (opcode & 0x30) {
case 0x00: {
if (sixteen) {
sprintf(buf + strlen(buf), " %2.2X%2.2X", t->insn[x], t->insn[x + 1]);
sprintf(right, "#$%4.4x", (t->insn[x] << 8) + t->insn[x + 1]);
x += 2;
} else {
sprintf(buf + strlen(buf), " %2.2X", t->insn[x]);
sprintf(right, "#$%2.2x", t->insn[x]);
x += 1;
}
break;
} case 0x10: {
sprintf(buf + strlen(buf), " %2.2X", t->insn[x]);
sprintf(right, "$%2.2x", t->insn[x++]);
memop = 1;
break;
} case 0x20: {
if (show_ind(t, &x, buf, right))
goto invalid;
memop = 1;
break;
} case 0x30: {
sprintf(buf + strlen(buf), " %2.2X%2.2X", t->insn[x], t->insn[x + 1]);
sprintf(right, "$%4.4x", (t->insn[x] << 8) + t->insn[x + 1]);
x += 2;
memop = 1;
break;
}
}
/* Operate F = A op B */
/* If A doesn't change, then we must F = A */
switch (opcode & 0x0F) {
case 0x00: /* SUB N,Z,V,C,H) */ {
insn = "SUB";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x01: /* CMP N,Z,V,C,H */ {
insn = "CMP";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x02: /* SBC N,Z,V,C,H */ {
insn = "SBC";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x03: /* SUBD/CMPD/CMPU or ADDD */ {
if (opcode & 0x40) {
insn = "ADD";
} else {
if (page3 || page2)
insn = "CMP";
else
insn = "SUB";
}
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
break;
} case 0x04: /* AND N,Z,V=0 */ {
insn = "AND";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x05: /* BIT N,Z,V=0 */ {
insn = "BIT";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x06: /* LDA N,Z,V=0 */ {
insn = "LD";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x07: /* STA N,Z,V=0 */ {
insn = "ST";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x08: /* EOR N,Z,V=0*/ {
insn = "EOR";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x09: /* ADC H,N,Z,V,C */ {
insn = "ADC";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x0A: /* ORA N,Z,V=0 */ {
insn = "ORA";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x0B: /* ADD H,N,Z,V,C */ {
insn = "ADD";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x0C: {
if (opcode & 0x40) { /* LDD */
insn = "LD";
} else { /* CMPX/CMPY/CMPS */
insn = "CMP";
}
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
break;
} case 0x0D: {
if (opcode & 0x40) { /* STD */
insn = "ST";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
} else { /* BSR/JSR */
if (!(opcode & 0x30)) { /* BSR */
insn = "BSR";
/* Replace immediate operand with branch target */
sprintf(right, "$%4.4x", 0xFFFF & (t->pc + 2 + (signed char)t->insn[x-1]));
left = "";
} else {
insn = "JSR";
left = "";
}
}
break;
} case 0x0E: { /* LDX/LDY/LDU/LDS */
insn = "LD";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
break;
} case 0x0F: { /* STX/STY/STU/STS */
insn = "ST";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
break;
}
}
} else if ((opcode & 0x40) || !(opcode & 0xF0)) { /* R.M.W. operations */
int memop = 0;
/* Fetch load operand */
if (!(opcode & 0xF0)) {
sprintf(buf + strlen(buf), " %2.2X", t->insn[x]);
sprintf(right, "$%2.2x", t->insn[x++]);
memop = 1;
} else {
switch (opcode & 0x30) {
case 0x00: {
left = "A";
break;
} case 0x10: {
left = "B";
break;
} case 0x20: {
memop = 1;
if (show_ind(t, &x, buf, right))
goto invalid;
break;
} case 0x30: {
memop = 1;
sprintf(buf + strlen(buf), " %2.2X%2.2X", t->insn[x], t->insn[x+1]);
sprintf(right, "$%4.4x", (t->insn[x] << 8) + t->insn[x+1]);
x += 2;
break;
}
}
}
/* Operate */
switch (opcode & 0x0F) {
case 0x00: /* NEG N, Z, V= ((f==0x80)?1:0), C= ((f==0)?1:0) */ {
insn = "NEG";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x01: /* ??? */ {
goto invalid;
break;
} case 0x02: /* ??? */ {
goto invalid;
break;
} case 0x03: /* COM N, Z, V=0, C=1 */ {
insn = "COM";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x04: /* LSR N=0,Z,C,V=N^C */ {
insn = "LSR";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x05: /* ??? */ {
goto invalid;
break;
} case 0x06: /* ROR N,Z,C,V=N^C */ {
insn = "ROR";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x07: /* ASR N,Z,C,V=N^C */ {
insn = "ASR";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x08: /* ASL N,Z,C,V=N^C */ {
insn = "ASL";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x09: /* ROL N,Z,C,V=N^C */ {
insn = "ROL";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x0A: /* DEC N,Z,V = (a=0x80?1:0) */ {
insn = "DEC";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);
break;
} case 0x0B: /* ??? */ {
goto invalid;
break;
} case 0x0C: /* INC N,Z,V = (a=0x7F?1:0) */ {
insn = "INC";
if ((t->status & 1) && memop)
sprintf(buf3, "EA=%4.4X%s D=%2.2X", t->ea, buf_ea, t->data);