Toc.md

1. Spinal Basic 1.1 quick-start 1.2 design-rules-check 1.3 Data-type 1.4 basic 1.4.1 Combinationa 1.4.2 Sequential 1.5 Stucturing 1.5.2 Width-propogate 1.5.3 Component-Function-area 1.5.3 ClockDomain 1.6 State-machine 1.7 Mem/Rom 1.8 IO

2. Example 1.1

3. Spinal Lib 2.1 Utils 2.2 FixPoint 2.3 Regif 2.4 pipeLine

4. Bus 3.1 concept 3.1 handshake 3.2 arbiter 3.3 outstanding 3.2 flow/stream 3.3 AMBA 3.3.1 APB 3.3.2 AHB 3.3.1 AXI 3.4 Tilelink 3.5 Peri 3.5.1 UART 3.5.2 SPI 3.5.3 I2C 3.5.4 USB 3.6 Other 3.6.1 ICB 3.6.2 WishBone

5. Soc Design 4.1 Architecture 4.2 4.2 pinseSec 4.3 VexRsicv 4.4 NaxRiscv

6. Simulation 6.1 enviroment Setup 6.1.1 Windows 6.1.2 MacOs 6.1.3 Linux 6.2 Boot Simulation 6.2.1 verilator 6.2.2 Vcs+fsdb 6.2.3 Modsim 6.2.4 GHDL/Iverilog 6.2.5 Vivado 6.2 boot a simulation 6.3 Simulation API 6.3.1 set/get/sleep 6.3.2 fork/join 6.5 SVM(SpinalVerificationMethodology) 6.5.1 Agent 6.5.1.1 Sequencer 6.5.1.2 Driver 6.5.1.3 Moniter 6.5.2 ScoreBoard

7. Landing 7.1 CPU 7.2 ANN(artificial neural network) 7.3 ISP 7.4 NetWork 7.4.1 SmartNIC 7.4.2 DPU 7.4.3 RDMA 7.5 baseband-communication 7.5.1 FFT 7.5.2 Viterbi 7.5.2 GPS/BD ....

8. Scala 8.1 scala-case-pattern 8.2 implicit 8.3 scala reflect 8.4 Macro 8.5 DataType

9. FunctionProgram 9.1 basic 9.3 advanced 9.3 usage

a. Concepet a.1 Config a.2 Plugin