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timing_report.txt
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timing_report.txt
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Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Fri Nov 17 00:01:22 2023
| Host : DESKTOP-DTP78NV running 64-bit major release (build 9200)
| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 -file D:/SOC/course-lab_4-2022.1/4_2_vivado/project_1/timing_report.txt
| Design : user_project_wrapper
| Device : 7z020-clg400
| Speed File : -1 PRODUCTION 1.12 2019-11-22
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (37)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (37)
-------------------------------
There are 37 input ports with no input delay specified. (HIGH)
la_data_in[65]
la_oenb[65]
wb_rst_i
wbs_cyc_i
wbs_dat_i[0]
wbs_dat_i[10]
wbs_dat_i[11]
wbs_dat_i[12]
wbs_dat_i[13]
wbs_dat_i[14]
wbs_dat_i[15]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[1]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[2]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_dat_i[3]
wbs_dat_i[4]
wbs_dat_i[5]
wbs_dat_i[6]
wbs_dat_i[7]
wbs_dat_i[8]
wbs_dat_i[9]
wbs_stb_i
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (9)
-------------------------------
There are 9 ports with no output delay specified. (HIGH)
la_data_out[0]
la_data_out[1]
la_data_out[2]
la_data_out[3]
wbs_ack_o
wbs_dat_o[0]
wbs_dat_o[1]
wbs_dat_o[2]
wbs_dat_o[3]
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
6.690 0.000 0 13 0.146 0.000 0 13 4.500 0.000 0 10
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
wb_clk_i {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
wb_clk_i 6.690 0.000 0 13 0.146 0.000 0 13 4.500 0.000 0 10
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
(none)
(none) wb_clk_i
(none) wb_clk_i
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: wb_clk_i
To Clock: wb_clk_i
Setup : 0 Failing Endpoints, Worst Slack 6.690ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 6.690ns (required time - arrival time)
Source: mprj/count_reg[1]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[0]/R
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.573ns (logic 0.773ns (30.043%) route 1.800ns (69.957%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[1]/Q
net (fo=7, unplaced) 1.000 3.934 mprj/io_out[1]
r mprj/count[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.229 r mprj/count[3]_i_1/O
net (fo=4, unplaced) 0.800 5.029 mprj/count[3]_i_1_n_0
FDRE r mprj/count_reg[0]/R
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[0]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_R) -0.557 11.719 mprj/count_reg[0]
-------------------------------------------------------------------
required time 11.719
arrival time -5.029
-------------------------------------------------------------------
slack 6.690
Slack (MET) : 6.690ns (required time - arrival time)
Source: mprj/count_reg[1]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[1]/R
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.573ns (logic 0.773ns (30.043%) route 1.800ns (69.957%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[1]/Q
net (fo=7, unplaced) 1.000 3.934 mprj/io_out[1]
r mprj/count[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.229 r mprj/count[3]_i_1/O
net (fo=4, unplaced) 0.800 5.029 mprj/count[3]_i_1_n_0
FDRE r mprj/count_reg[1]/R
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[1]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_R) -0.557 11.719 mprj/count_reg[1]
-------------------------------------------------------------------
required time 11.719
arrival time -5.029
-------------------------------------------------------------------
slack 6.690
Slack (MET) : 6.690ns (required time - arrival time)
Source: mprj/count_reg[1]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[2]/R
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.573ns (logic 0.773ns (30.043%) route 1.800ns (69.957%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[1]/Q
net (fo=7, unplaced) 1.000 3.934 mprj/io_out[1]
r mprj/count[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.229 r mprj/count[3]_i_1/O
net (fo=4, unplaced) 0.800 5.029 mprj/count[3]_i_1_n_0
FDRE r mprj/count_reg[2]/R
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[2]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_R) -0.557 11.719 mprj/count_reg[2]
-------------------------------------------------------------------
required time 11.719
arrival time -5.029
-------------------------------------------------------------------
slack 6.690
Slack (MET) : 6.690ns (required time - arrival time)
Source: mprj/count_reg[1]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[3]/R
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.573ns (logic 0.773ns (30.043%) route 1.800ns (69.957%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[1]/Q
net (fo=7, unplaced) 1.000 3.934 mprj/io_out[1]
r mprj/count[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.229 r mprj/count[3]_i_1/O
net (fo=4, unplaced) 0.800 5.029 mprj/count[3]_i_1_n_0
FDRE r mprj/count_reg[3]/R
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[3]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_R) -0.557 11.719 mprj/count_reg[3]
-------------------------------------------------------------------
required time 11.719
arrival time -5.029
-------------------------------------------------------------------
slack 6.690
Slack (MET) : 8.294ns (required time - arrival time)
Source: mprj/count_reg[0]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[3]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.570ns (logic 0.797ns (50.764%) route 0.773ns (49.236%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[0]/Q
net (fo=6, unplaced) 0.773 3.707 mprj/io_out[0]
r mprj/count[3]_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.319 4.026 r mprj/count[3]_i_3/O
net (fo=1, unplaced) 0.000 4.026 mprj/p_0_in[3]
FDRE r mprj/count_reg[3]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[3]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 mprj/count_reg[3]
-------------------------------------------------------------------
required time 12.320
arrival time -4.026
-------------------------------------------------------------------
slack 8.294
Slack (MET) : 8.318ns (required time - arrival time)
Source: mprj/count_reg[2]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/READY_reg/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.546ns (logic 0.773ns (50.000%) route 0.773ns (50.000%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[2]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[2]/Q
net (fo=6, unplaced) 0.773 3.707 mprj/io_out[2]
r mprj/READY_i_1/I3
LUT6 (Prop_lut6_I3_O) 0.295 4.002 r mprj/READY_i_1/O
net (fo=1, unplaced) 0.000 4.002 mprj/READY_i_1_n_0
FDRE r mprj/READY_reg/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/READY_reg/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 mprj/READY_reg
-------------------------------------------------------------------
required time 12.320
arrival time -4.002
-------------------------------------------------------------------
slack 8.318
Slack (MET) : 8.318ns (required time - arrival time)
Source: mprj/count_reg[0]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[2]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.546ns (logic 0.773ns (50.000%) route 0.773ns (50.000%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[0]/Q
net (fo=6, unplaced) 0.773 3.707 mprj/io_out[0]
r mprj/count[2]_i_1/I0
LUT3 (Prop_lut3_I0_O) 0.295 4.002 r mprj/count[2]_i_1/O
net (fo=1, unplaced) 0.000 4.002 mprj/p_0_in[2]
FDRE r mprj/count_reg[2]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[2]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 mprj/count_reg[2]
-------------------------------------------------------------------
required time 12.320
arrival time -4.002
-------------------------------------------------------------------
slack 8.318
Slack (MET) : 8.368ns (required time - arrival time)
Source: mprj/count_reg[1]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: wb_ctrl_o_reg[1]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.496ns (logic 0.795ns (53.142%) route 0.701ns (46.858%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[1]/Q
net (fo=7, unplaced) 0.701 3.635 mprj/io_out[1]
r mprj/wb_ctrl_o[1]_i_1/I3
LUT4 (Prop_lut4_I3_O) 0.317 3.952 r mprj/wb_ctrl_o[1]_i_1/O
net (fo=1, unplaced) 0.000 3.952 mprj_n_6
FDRE r wb_ctrl_o_reg[1]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r wb_ctrl_o_reg[1]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 wb_ctrl_o_reg[1]
-------------------------------------------------------------------
required time 12.320
arrival time -3.952
-------------------------------------------------------------------
slack 8.368
Slack (MET) : 8.375ns (required time - arrival time)
Source: mprj/count_reg[3]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: wb_ctrl_o_reg[3]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.489ns (logic 0.795ns (53.392%) route 0.694ns (46.608%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[3]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[3]/Q
net (fo=5, unplaced) 0.694 3.628 mprj/io_out[3]
r mprj/wb_ctrl_o[3]_i_2/I3
LUT4 (Prop_lut4_I3_O) 0.317 3.945 r mprj/wb_ctrl_o[3]_i_2/O
net (fo=1, unplaced) 0.000 3.945 mprj_n_8
FDRE r wb_ctrl_o_reg[3]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r wb_ctrl_o_reg[3]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 wb_ctrl_o_reg[3]
-------------------------------------------------------------------
required time 12.320
arrival time -3.945
-------------------------------------------------------------------
slack 8.375
Slack (MET) : 8.393ns (required time - arrival time)
Source: mprj/count_reg[0]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: wb_ctrl_o_reg[0]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.471ns (logic 0.773ns (52.549%) route 0.698ns (47.451%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.584 2.456 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r mprj/count_reg[0]/Q
net (fo=6, unplaced) 0.698 3.632 mprj/io_out[0]
r mprj/wb_ctrl_o[0]_i_1/I3
LUT4 (Prop_lut4_I3_O) 0.295 3.927 r mprj/wb_ctrl_o[0]_i_1/O
net (fo=1, unplaced) 0.000 3.927 mprj_n_1
FDRE r wb_ctrl_o_reg[0]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r wb_ctrl_o_reg[0]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 wb_ctrl_o_reg[0]
-------------------------------------------------------------------
required time 12.320
arrival time -3.927
-------------------------------------------------------------------
slack 8.393
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.146ns (arrival time - required time)
Source: mprj/count_reg[0]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[0]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 0.390ns (logic 0.245ns (62.888%) route 0.145ns (37.112%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.032ns
Source Clock Delay (SCD): 0.678ns
Clock Pessimism Removal (CPR): 0.210ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.200 0.200 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.538 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.026 0.564 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.114 0.678 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.147 0.825 f mprj/count_reg[0]/Q
net (fo=6, unplaced) 0.145 0.969 mprj/io_out[0]
f mprj/count[0]_i_1/I0
LUT1 (Prop_lut1_I0_O) 0.098 1.067 r mprj/count[0]_i_1/O
net (fo=1, unplaced) 0.000 1.067 mprj/p_0_in[0]
FDRE r mprj/count_reg[0]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.389 0.389 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.744 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.029 0.773 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.259 1.032 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[0]/C
clock pessimism -0.210 0.823
FDRE (Hold_fdre_C_D) 0.099 0.922 mprj/count_reg[0]
-------------------------------------------------------------------
required time -0.922
arrival time 1.067
-------------------------------------------------------------------
slack 0.146
Slack (MET) : 0.146ns (arrival time - required time)
Source: mprj/count_reg[2]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: mprj/count_reg[2]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 0.390ns (logic 0.245ns (62.888%) route 0.145ns (37.112%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.032ns
Source Clock Delay (SCD): 0.678ns
Clock Pessimism Removal (CPR): 0.210ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.200 0.200 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.538 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.026 0.564 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.114 0.678 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[2]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.147 0.825 r mprj/count_reg[2]/Q
net (fo=6, unplaced) 0.145 0.969 mprj/io_out[2]
r mprj/count[2]_i_1/I2
LUT3 (Prop_lut3_I2_O) 0.098 1.067 r mprj/count[2]_i_1/O
net (fo=1, unplaced) 0.000 1.067 mprj/p_0_in[2]
FDRE r mprj/count_reg[2]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.389 0.389 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.744 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.029 0.773 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=9, unplaced) 0.259 1.032 mprj/wb_clk_i_IBUF_BUFG
FDRE r mprj/count_reg[2]/C
clock pessimism -0.210 0.823