added clock divider

info.yaml

@@ -21,6 +21,7 @@ project:
     - "controller.v"
     - "rng.v"
     - "timer.v"
+    - "clk_div.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/clk_div.v

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2023 Iron Violet LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//============================================================================//
+// Clock Divider
+//============================================================================//
+
+`define default_netname none
+
+module clk_div #(
+  parameter  FREQ_IN  = 50_000_000,
+  parameter  FREQ_OUT = 10_000
+)(
+  input      CLK,
+  input      RST_N,
+  output reg CLK_OUT
+);
+  parameter DIV = FREQ_IN / FREQ_OUT;
+
+  reg [$clog2(DIV)-1:0] cntr;
+
+  // clock counter
+  always @(posedge CLK or negedge RST_N) begin
+    if (!RST_N) begin
+      cntr <= 0;
+    end else if (cntr >= (DIV-1)) begin
+      cntr <= 0;
+    end else begin
+      cntr <= cntr + 1;
+    end
+  end
+
+  // divided clock
+  always @(posedge CLK or negedge RST_N) begin
+    if (!RST_N) begin
+      CLK_OUT <= 0;
+    end else if (cntr < DIV/2) begin
+      CLK_OUT <= 1;
+    end else begin
+      CLK_OUT <= 0;
+    end
+  end
+
+endmodule : clk_div  

src/project.v

@@ -39,6 +39,17 @@ module tt_um_iron_violet_simon (
   assign uo_out[3] = lamp_ena &  lamp_out[1] &  lamp_out[0];
 
   wire timer_go;
+
+  wire clk_10khz;
+
+  clk_div #(
+    .FREQ_IN  (50_000_000),
+    .FREQ_OUT (10_000)
+  ) clk_div_u1 (
+    .CLK      (clk),
+    .RST_N    (rst_n),
+    .CLK_OUT  (clk_10khz)
+  );
 
   io_sync io_sync_u1 (
     .CLK      (clk),