From 49e22b825a94570387ac6aa70bd36d2edf10a710 Mon Sep 17 00:00:00 2001 From: Jay Vasanth Date: Tue, 19 Apr 2022 17:55:11 -0400 Subject: [PATCH] drivers: clock-control: Microchip MEC172x adjust clock based on OTP Microchip MEC172x CPU and fast peripheral (QMSPI and PK) are clock source is based upon an OTP setting. Add logic to adjust clock source based on OTP value. If the OTP value is ever changed this fix will allow calcluation of correct clock rate. Signed-off-by: Jay Vasanth --- drivers/clock_control/clock_control_mchp_xec.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clock_control/clock_control_mchp_xec.c b/drivers/clock_control/clock_control_mchp_xec.c index f8bc4cfc30efcc..1e0d9b44d6b49c 100644 --- a/drivers/clock_control/clock_control_mchp_xec.c +++ b/drivers/clock_control/clock_control_mchp_xec.c @@ -559,11 +559,19 @@ static int xec_clock_control_get_subsys_rate(const struct device *dev, switch (bus) { case MCHP_XEC_PCR_CLK_CORE: case MCHP_XEC_PCR_CLK_PERIPH_FAST: - *rate = MHZ(96); + if (pcr->TURBO_CLK & MCHP_PCR_TURBO_CLK_96M) { + *rate = MHZ(96); + } else { + *rate = MHZ(48); + } break; case MCHP_XEC_PCR_CLK_CPU: /* if PCR PROC_CLK_CTRL is 0 the chip is not running */ - *rate = MHZ(96) / pcr->PROC_CLK_CTRL; + if (pcr->TURBO_CLK & MCHP_PCR_TURBO_CLK_96M) { + *rate = MHZ(96) / pcr->PROC_CLK_CTRL; + } else { + *rate = MHZ(48) / pcr->PROC_CLK_CTRL; + } break; case MCHP_XEC_PCR_CLK_BUS: case MCHP_XEC_PCR_CLK_PERIPH: