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ensure that when we do the ARM side of an i1 store, only 0 or 1 is stored
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rig llvm-reduce to be a fuzzer
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refactor so instructions go into separate files and use a proper API
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support jump tables, requires symbolic register contents
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anytime SP is updated, assert that it's a multiple of 16
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we're making a mess out of handling layoutinfo and targettriple
- let's use the included info by default
- but have a flag to force this, for processing bitcode without ARM target info
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assert that stack memory is not trashed
- saved ret addr
- saved FP
- what else?
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stop using instrs_64 and friends, just use the register numbers in the instructions to get the correct-sized operands
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support function calls
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size the stack correctly, instead of hard-coding a size
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write a script that finds test cases for instructions where we lack a test
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find a good set of opt passes that doesn't trigger middle-end FP bugs
- then turn FP back on and keep adding instructions
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mark parameters noundef?
- probably not necessary since we're turning on Alive2's flags to disable poison and undef inputs
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more vector instructions
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more memory operations
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more FP operations