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we can assume the input is posiive -> ALL RELU LAY... #28

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github-actions bot opened this issue Mar 23, 2020 · 0 comments

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todo

github-actions bot commented Mar 23, 2020

we can assume the input is posiive -> ALL RELU LAYERS! Maybe some input checks or warning would be good?
https://github.com/marbleton/FPGA_MNIST/blob/6555feb45d01be05ffa8c043cd5ebc2e712df655/vivado/NN_IP/EggNet_1.0/src/Conv_Channel/3x3_shift_kernel.vhd#L55

github-actions bot added the todo label

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