LUT and CARRY over utilization

[andreaportaluri]

I'd like to congratulate you for the very good project you built. However, an issue arises when I try to implement your .vhd code into the very same FPGA part you used: the amount of LUTs necessary is much higher than the one available on the Z7020 (almost 130k vs. 52k, respectively). I also tried to reduce it by means of synthesis constraints and vhdl attributes but very little has changed. Did you witness the same scenario? Any suggestion about it?
Thank you very much.

[LukiBa]

Hi @andreaportaluri
Did you try to reduce the bit width of the network?