Bit fiddling / slicing help

[kenkendk]

In low-level logic it is common that words are split into bits and bit regions.
In VHDL this is nicely supported with slice ranges, similar to how Python supports it.

To support this we should add two features to SME.

The first feature is with named fields, and could look like this:

public interface IBitSplitter<T> 
{
    T Value { get; set; }
}

public interface IMyCombi : IBitSplitter<byte>
{
    [BitOffset(0)]
    UInt3 Lead { get; set; }

    [BitOffset(0)]
    bool LeadSign { get; set; }

    [BitOffset(3)]
    UInt4 Control { get; set; }
}

The runtime will then create a struct that implements the interface correctly and allows the aliasing of the bits. The interface can then be used in a Bus definition as well.

To further help with bit fiddling, a number of support methods should be added:

public static UInt4 Slice4(this int value, uint offset, uint count = 4) { ... };
public static UInt8 Slice8(this int value, uint offset, uint count = 8) { ... };
...

The implementation in C# is simply a shift-n-mask, but the VHDL generator can emit slice expressions if the arguments are constant, and revert to shift-n-mask if the argument values cannot be determined statically.

A more general slice function could also be something like:

public static ulong Slice(this ulong value, uint offset, uint count) { ... };

This will return 64 bit values, but the VHDL vendor tools will usually optimize the unused bits away.

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