Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Create unittests for range-limited types #13

Open
kenkendk opened this issue Aug 11, 2017 · 0 comments
Open

Create unittests for range-limited types #13

kenkendk opened this issue Aug 11, 2017 · 0 comments

Comments

@kenkendk
Copy link
Owner

kenkendk commented Aug 11, 2017

Add an example that uses UInt2, UInt3, .. and tests that they work correctly in the full range (i.e. overflow/undeflow them). The test should verify both the simulation and generated C++ and VHDL code.


Want to back this issue? Post a bounty on it! We accept bounties via Bountysource.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant