Ignore case for VHDL

kevinpt · Feb 16, 2018 · be7cdab · be7cdab
1 parent 3560160
commit be7cdab
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
@@ -142,7 +142,7 @@
   ],
 }
 
-VhdlLexer = MiniLexer(vhdl_tokens)
+VhdlLexer = MiniLexer(vhdl_tokens, flags=re.MULTILINE | re.IGNORECASE)
 
 
 class VhdlObject(object):