From 88ae9f90e4324a76d80981f79813d18e6daaefde Mon Sep 17 00:00:00 2001 From: root Date: Wed, 30 Oct 2019 16:21:48 +0100 Subject: [PATCH 1/2] fix typo in README Signed-off-by: jbaltes --- README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index ad0982f..8560563 100644 --- a/README.md +++ b/README.md @@ -77,14 +77,14 @@ Examples: The naming convention is ``. Where `` is one of the following protocols: -| Character | Description | -| --------- | ----------------- | -| `1` | PCIe x1 lane | -| `2` | PCIe x2 lane | -| `s` | SATA lane | -| `g` | SGMII lane | -| `q` | QSGMII lane | -| `_` | lane not avalable | +| Character | Description | +| --------- | ------------------ | +| `1` | PCIe x1 lane | +| `2` | PCIe x2 lane | +| `s` | SATA lane | +| `g` | SGMII lane | +| `q` | QSGMII lane | +| `_` | lane not available | All variants only supports different SerDes protocols on SMARC PCIe A/B lanes. Please note that the protocols in (brackets) are optional features From beb70964000da141f37dfd41215020b08967016e Mon Sep 17 00:00:00 2001 From: root Date: Wed, 30 Oct 2019 16:47:09 +0100 Subject: [PATCH 2/2] add limitation note for SSC Signed-off-by: jbaltes --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index 8560563..2ae03d0 100644 --- a/README.md +++ b/README.md @@ -94,6 +94,9 @@ always have QSGMII on the PCIe D lane. Due to a limitation of the LS1028A SoC, PCIe Gen3 cannot be used simultaneously with SATA. Therefore, if a RCW with SATA is programmed, PCIe will only negotiate to to PCIe Gen1 or Gen2. +If spread spectrum clock (SSC) is intended to use for PCIe, +the SGMII lanes will not work, because PCIe and SGMII use the same PLL and +SGMII can not work with SSC. ### Variant 2: Dual TSN port module