From 4fc7ae47cada97acc17c115fa26e00a6d5e470fb Mon Sep 17 00:00:00 2001 From: Heiko Thiery Date: Thu, 23 Sep 2021 21:42:47 +0200 Subject: [PATCH] README.md: fix CPLD NVM bits description table Signed-off-by: Heiko Thiery --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 25e5d42..f68f032 100644 --- a/README.md +++ b/README.md @@ -50,6 +50,7 @@ places. By default, the payload is loaded from the SPI flash. The user can set another location by programming the NVM bits 15 and 14 inside the CPLD. | CPLD NVM bits | Bootloader location | +| --------------- | --------------------------- | | `2'b11`, `2b10` | FSPI flash CS#0 @`21_0000h` | | `2'b01` | FSPI flash CS#1 @`1_0000h` | | `2'b00` | DSPI flash CS#0 @`1_0000h` |