diff --git a/.github/workflows/release-lit.yml b/.github/workflows/release-lit.yml index 36b0b6edd518fc..0316ba406041d6 100644 --- a/.github/workflows/release-lit.yml +++ b/.github/workflows/release-lit.yml @@ -58,7 +58,7 @@ jobs: cd llvm/utils/lit # Remove 'dev' suffix from lit version. sed -i 's/ + "dev"//g' lit/__init__.py - python3 setup.py sdist + python3 setup.py sdist bdist_wheel - name: Upload lit to test.pypi.org uses: pypa/gh-action-pypi-publish@release/v1 diff --git a/clang/cmake/caches/Release.cmake b/clang/cmake/caches/Release.cmake index 1ca9138b980731..bd1f688d61a7ea 100644 --- a/clang/cmake/caches/Release.cmake +++ b/clang/cmake/caches/Release.cmake @@ -4,7 +4,7 @@ # General Options set(LLVM_RELEASE_ENABLE_LTO THIN CACHE STRING "") -set(LLVM_RELEASE_ENABLE_PGO ON CACHE BOOL "") +set(LLVM_RELEASE_ENABLE_PGO OFF CACHE BOOL "") set(CMAKE_BUILD_TYPE RELEASE CACHE STRING "") diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 58838b01b4fd7c..dbf2dd2120fb69 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -1590,6 +1590,7 @@ def RegCall : DeclOrTypeAttr { } def Final : InheritableAttr { + let CanPrintOnLeft = 0; let Spellings = [CustomKeyword<"final">, CustomKeyword<"sealed">]; let Accessors = [Accessor<"isSpelledAsSealed", [CustomKeyword<"sealed">]>]; let SemaHandler = 0; @@ -2472,6 +2473,7 @@ def Overloadable : Attr { } def Override : InheritableAttr { + let CanPrintOnLeft = 0; let Spellings = [CustomKeyword<"override">]; let SemaHandler = 0; // Omitted from docs, since this is language syntax, not an attribute, as far diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index d0c4273cfc7e58..4d482e6543d6f5 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -3450,10 +3450,11 @@ void TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const { for (AnnotatedLine *ChildLine : Line.Children) calculateFormattingInformation(*ChildLine); - Line.First->TotalLength = - Line.First->IsMultiline ? Style.ColumnLimit - : Line.FirstStartColumn + Line.First->ColumnWidth; - FormatToken *Current = Line.First->Next; + auto *First = Line.First; + First->TotalLength = First->IsMultiline + ? Style.ColumnLimit + : Line.FirstStartColumn + First->ColumnWidth; + FormatToken *Current = First->Next; bool InFunctionDecl = Line.MightBeFunctionDecl; bool AlignArrayOfStructures = (Style.AlignArrayOfStructures != FormatStyle::AIAS_None && @@ -3475,16 +3476,15 @@ void TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const { if (const bool IsCtorOrDtor = Tok->is(TT_CtorDtorDeclName); IsCtorOrDtor || isFunctionDeclarationName(Style.isCpp(), *Tok, Line, ClosingParen)) { - if (!IsCtorOrDtor) { - LineIsFunctionDeclaration = true; + if (!IsCtorOrDtor) Tok->setFinalizedType(TT_FunctionDeclarationName); - } + LineIsFunctionDeclaration = true; SeenName = true; break; } } - if (IsCpp && LineIsFunctionDeclaration && + if (IsCpp && (LineIsFunctionDeclaration || First->is(TT_CtorDtorDeclName)) && Line.endsWith(tok::semi, tok::r_brace)) { auto *Tok = Line.Last->Previous; while (Tok->isNot(tok::r_brace)) @@ -3507,7 +3507,7 @@ void TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const { if (IsCpp) { if (!LineIsFunctionDeclaration) { // Annotate */&/&& in `operator` function calls as binary operators. - for (const auto *Tok = Line.First; Tok; Tok = Tok->Next) { + for (const auto *Tok = First; Tok; Tok = Tok->Next) { if (Tok->isNot(tok::kw_operator)) continue; do { @@ -3644,7 +3644,7 @@ void TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const { calculateUnbreakableTailLengths(Line); unsigned IndentLevel = Line.Level; - for (Current = Line.First; Current; Current = Current->Next) { + for (Current = First; Current; Current = Current->Next) { if (Current->Role) Current->Role->precomputeFormattingInfos(Current); if (Current->MatchingParen && diff --git a/clang/lib/Headers/__stddef_unreachable.h b/clang/lib/Headers/__stddef_unreachable.h index 518580c92d3f5d..61df43e9732f8a 100644 --- a/clang/lib/Headers/__stddef_unreachable.h +++ b/clang/lib/Headers/__stddef_unreachable.h @@ -7,6 +7,8 @@ *===-----------------------------------------------------------------------=== */ +#ifndef __cplusplus + /* * When -fbuiltin-headers-in-system-modules is set this is a non-modular header * and needs to behave as if it was textual. @@ -15,3 +17,5 @@ (__has_feature(modules) && !__building_module(_Builtin_stddef)) #define unreachable() __builtin_unreachable() #endif + +#endif diff --git a/clang/test/AST/ast-dump-override-final.cpp b/clang/test/AST/ast-dump-override-final.cpp new file mode 100644 index 00000000000000..c1cee6b01565f6 --- /dev/null +++ b/clang/test/AST/ast-dump-override-final.cpp @@ -0,0 +1,20 @@ +// This file contain tests to check if override and final are dumped in the +// correct positions. + +// RUN: %clang_cc1 -ast-print -x c++ %s -o - | FileCheck %s + +// CHECK: class A { +class A { + // CHECK-NEXT: virtual void f(); + virtual void f(); + + // CHECK-NEXT: virtual void g() final; + virtual void g() final; +} AA; + +// CHECK: class B : public A { +class B : public A { + // CHECK-NEXT: virtual void f() override { + virtual void f() override { + }; +} B; diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index 67678c18963b1f..c72c9384ff91d6 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -2595,6 +2595,20 @@ TEST_F(TokenAnnotatorTest, BraceKind) { EXPECT_TOKEN(Tokens[4], tok::l_brace, TT_FunctionLBrace); EXPECT_BRACE_KIND(Tokens[4], BK_Block); EXPECT_BRACE_KIND(Tokens[6], BK_Block); + + Tokens = annotate("struct Foo {\n" + " Foo() {};\n" + " ~Foo() {};\n" + "};"); + ASSERT_EQ(Tokens.size(), 19u) << Tokens; + EXPECT_TOKEN(Tokens[3], tok::identifier, TT_CtorDtorDeclName); + EXPECT_TOKEN(Tokens[6], tok::l_brace, TT_FunctionLBrace); + EXPECT_BRACE_KIND(Tokens[6], BK_Block); + EXPECT_BRACE_KIND(Tokens[7], BK_Block); + EXPECT_TOKEN(Tokens[10], tok::identifier, TT_CtorDtorDeclName); + EXPECT_TOKEN(Tokens[13], tok::l_brace, TT_FunctionLBrace); + EXPECT_BRACE_KIND(Tokens[13], BK_Block); + EXPECT_BRACE_KIND(Tokens[14], BK_Block); } TEST_F(TokenAnnotatorTest, StreamOperator) { diff --git a/compiler-rt/lib/builtins/riscv/restore.S b/compiler-rt/lib/builtins/riscv/restore.S index 73f64a920d6698..6f43842c8ca684 100644 --- a/compiler-rt/lib/builtins/riscv/restore.S +++ b/compiler-rt/lib/builtins/riscv/restore.S @@ -22,6 +22,8 @@ #if __riscv_xlen == 32 +#ifndef __riscv_32e + .globl __riscv_restore_12 .type __riscv_restore_12,@function __riscv_restore_12: @@ -86,8 +88,29 @@ __riscv_restore_0: addi sp, sp, 16 ret +#else + + .globl __riscv_restore_2 + .type __riscv_restore_2,@function + .globl __riscv_restore_1 + .type __riscv_restore_1,@function + .globl __riscv_restore_0 + .type __riscv_restore_0,@function +__riscv_restore_2: +__riscv_restore_1: +__riscv_restore_0: + lw s1, 0(sp) + lw s0, 4(sp) + lw ra, 8(sp) + addi sp, sp, 12 + ret + +#endif + #elif __riscv_xlen == 64 +#ifndef __riscv_64e + .globl __riscv_restore_12 .type __riscv_restore_12,@function __riscv_restore_12: @@ -161,6 +184,25 @@ __riscv_restore_0: addi sp, sp, 16 ret +#else + + .globl __riscv_restore_2 + .type __riscv_restore_2,@function + .globl __riscv_restore_1 + .type __riscv_restore_1,@function + .globl __riscv_restore_0 + .type __riscv_restore_0,@function +__riscv_restore_2: +__riscv_restore_1: +__riscv_restore_0: + ld s1, 0(sp) + ld s0, 8(sp) + ld ra, 16(sp) + addi sp, sp, 24 + ret + +#endif + #else # error "xlen must be 32 or 64 for save-restore implementation #endif diff --git a/compiler-rt/lib/builtins/riscv/save.S b/compiler-rt/lib/builtins/riscv/save.S index 85501aeb4c2e93..3e044179ff7f1d 100644 --- a/compiler-rt/lib/builtins/riscv/save.S +++ b/compiler-rt/lib/builtins/riscv/save.S @@ -18,6 +18,8 @@ #if __riscv_xlen == 32 +#ifndef __riscv_32e + .globl __riscv_save_12 .type __riscv_save_12,@function __riscv_save_12: @@ -92,8 +94,29 @@ __riscv_save_0: sw ra, 12(sp) jr t0 +#else + + .globl __riscv_save_2 + .type __riscv_save_2,@function + .globl __riscv_save_1 + .type __riscv_save_1,@function + .globl __riscv_save_0 + .type __riscv_save_0,@function +__riscv_save_2: +__riscv_save_1: +__riscv_save_0: + addi sp, sp, -12 + sw s1, 0(sp) + sw s0, 4(sp) + sw ra, 8(sp) + jr t0 + +#endif + #elif __riscv_xlen == 64 +#ifndef __riscv_64e + .globl __riscv_save_12 .type __riscv_save_12,@function __riscv_save_12: @@ -181,6 +204,25 @@ __riscv_save_0: sd ra, 8(sp) jr t0 +#else + + .globl __riscv_save_2 + .type __riscv_save_2,@function + .globl __riscv_save_1 + .type __riscv_save_1,@function + .globl __riscv_save_0 + .type __riscv_save_0,@function +__riscv_save_2: +__riscv_save_1: +__riscv_save_0: + addi sp, sp, -24 + sd s1, 0(sp) + sd s0, 8(sp) + sd ra, 16(sp) + jr t0 + +#endif + #else # error "xlen must be 32 or 64 for save-restore implementation #endif diff --git a/libcxx/include/__format/formatter_floating_point.h b/libcxx/include/__format/formatter_floating_point.h index 6802a8b7bd4ca3..46a090a787ae28 100644 --- a/libcxx/include/__format/formatter_floating_point.h +++ b/libcxx/include/__format/formatter_floating_point.h @@ -689,7 +689,7 @@ __format_floating_point(_Tp __value, _FormatContext& __ctx, __format_spec::__par // Let P equal the precision if nonzero, 6 if the precision is not // specified, or 1 if the precision is 0. Then, if a conversion with // style E would have an exponent of X: - int __p = std::max(1, (__specs.__has_precision() ? __specs.__precision_ : 6)); + int __p = std::max(1, (__specs.__has_precision() ? __specs.__precision_ : 6)); if (__result.__exponent == __result.__last) // if P > X >= -4, the conversion is with style f or F and precision P - 1 - X. // By including the radix point it calculates P - (1 + X) diff --git a/libcxx/include/stddef.h b/libcxx/include/stddef.h index 887776b150e49d..1583e78e3739ba 100644 --- a/libcxx/include/stddef.h +++ b/libcxx/include/stddef.h @@ -7,18 +7,6 @@ // //===----------------------------------------------------------------------===// -#if defined(__need_ptrdiff_t) || defined(__need_size_t) || defined(__need_wchar_t) || defined(__need_NULL) || \ - defined(__need_wint_t) - -# if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) -# pragma GCC system_header -# endif - -# include_next - -#elif !defined(_LIBCPP_STDDEF_H) -# define _LIBCPP_STDDEF_H - /* stddef.h synopsis @@ -36,15 +24,18 @@ */ -# include <__config> +#include <__config> -# if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) -# pragma GCC system_header -# endif +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif -# if __has_include_next() -# include_next -# endif +// Note: This include is outside of header guards because we sometimes get included multiple times +// with different defines and the underlying will know how to deal with that. +#include_next + +#ifndef _LIBCPP_STDDEF_H +# define _LIBCPP_STDDEF_H # ifdef __cplusplus typedef decltype(nullptr) nullptr_t; diff --git a/lld/COFF/Chunks.cpp b/lld/COFF/Chunks.cpp index 39f4575031be54..e2074932bc466e 100644 --- a/lld/COFF/Chunks.cpp +++ b/lld/COFF/Chunks.cpp @@ -652,6 +652,13 @@ void SectionChunk::getRuntimePseudoRelocs( dyn_cast_or_null(file->getSymbol(rel.SymbolTableIndex)); if (!target || !target->isRuntimePseudoReloc) continue; + // If the target doesn't have a chunk allocated, it may be a + // DefinedImportData symbol which ended up unnecessary after GC. + // Normally we wouldn't eliminate section chunks that are referenced, but + // references within DWARF sections don't count for keeping section chunks + // alive. Thus such dangling references in DWARF sections are expected. + if (!target->getChunk()) + continue; int sizeInBits = getRuntimePseudoRelocSize(rel.Type, file->ctx.config.machine); if (sizeInBits == 0) { diff --git a/lld/test/COFF/autoimport-gc.s b/lld/test/COFF/autoimport-gc.s new file mode 100644 index 00000000000000..fef6c02eba82f9 --- /dev/null +++ b/lld/test/COFF/autoimport-gc.s @@ -0,0 +1,41 @@ +# REQUIRES: x86 +# RUN: split-file %s %t.dir + +# RUN: llvm-mc -triple=x86_64-windows-gnu %t.dir/lib.s -filetype=obj -o %t.dir/lib.obj +# RUN: lld-link -out:%t.dir/lib.dll -dll -entry:DllMainCRTStartup %t.dir/lib.obj -lldmingw -implib:%t.dir/lib.lib + +# RUN: llvm-mc -triple=x86_64-windows-gnu %t.dir/main.s -filetype=obj -o %t.dir/main.obj +# RUN: lld-link -lldmingw -out:%t.dir/main.exe -entry:main %t.dir/main.obj %t.dir/lib.lib -opt:ref -debug:dwarf + +#--- main.s + .global main + .section .text$main,"xr",one_only,main +main: + ret + + .global other + .section .text$other,"xr",one_only,other +other: + movq .refptr.variable(%rip), %rax + movl (%rax), %eax + ret + + .section .rdata$.refptr.variable,"dr",discard,.refptr.variable + .global .refptr.variable +.refptr.variable: + .quad variable + + .section .debug_info + .long 1 + .quad variable + .long 2 + +#--- lib.s + .global variable + .global DllMainCRTStartup + .text +DllMainCRTStartup: + ret + .data +variable: + .long 42 diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 253f3943c3b51f..98dbab810bacbf 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR) set(LLVM_VERSION_MINOR 1) endif() if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 3) + set(LLVM_VERSION_PATCH 4) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) set(LLVM_VERSION_SUFFIX) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 7a7ddc59ba985d..74b0439da7fc58 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -5499,6 +5499,8 @@ RISC-V: Sparc: +- ``L``: Print the low-order register of a two-register operand. +- ``H``: Print the high-order register of a two-register operand. - ``r``: No effect. SystemZ: diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index d0c27cae0dff99..72b6dfa181e86d 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -439,7 +439,8 @@ static Value *threadBinOpOverSelect(Instruction::BinaryOps Opcode, Value *LHS, // Check that the simplified value has the form "X op Y" where "op" is the // same as the original operation. Instruction *Simplified = dyn_cast(FV ? FV : TV); - if (Simplified && Simplified->getOpcode() == unsigned(Opcode)) { + if (Simplified && Simplified->getOpcode() == unsigned(Opcode) && + !Simplified->hasPoisonGeneratingFlags()) { // The value that didn't simplify is "UnsimplifiedLHS op UnsimplifiedRHS". // We already know that "op" is the same as for the simplified value. See // if the operands match too. If so, return the simplified value. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 3135ec73a99e76..e806e0f0731f23 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3575,6 +3575,11 @@ static SDValue combineCarryDiamond(SelectionDAG &DAG, const TargetLowering &TLI, return SDValue(); if (Opcode != ISD::UADDO && Opcode != ISD::USUBO) return SDValue(); + // Guarantee identical type of CarryOut + EVT CarryOutType = N->getValueType(0); + if (CarryOutType != Carry0.getValue(1).getValueType() || + CarryOutType != Carry1.getValue(1).getValueType()) + return SDValue(); // Canonicalize the add/sub of A and B (the top node in the above ASCII art) // as Carry0 and the add/sub of the carry in as Carry1 (the middle node). @@ -3622,7 +3627,7 @@ static SDValue combineCarryDiamond(SelectionDAG &DAG, const TargetLowering &TLI, // TODO: match other operations that can merge flags (ADD, etc) DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0)); if (N->getOpcode() == ISD::AND) - return DAG.getConstant(0, DL, MVT::i1); + return DAG.getConstant(0, DL, CarryOutType); return Merged.getValue(1); } diff --git a/llvm/lib/IR/ConstantRange.cpp b/llvm/lib/IR/ConstantRange.cpp index cbb64b299e648e..f105bdb4816aa0 100644 --- a/llvm/lib/IR/ConstantRange.cpp +++ b/llvm/lib/IR/ConstantRange.cpp @@ -746,7 +746,7 @@ ConstantRange ConstantRange::castOp(Instruction::CastOps CastOp, Min = Min.zext(ResultBitWidth); Max = Max.zext(ResultBitWidth); } - return ConstantRange(std::move(Min), std::move(Max)); + return getNonEmpty(std::move(Min), std::move(Max) + 1); } case Instruction::SIToFP: { // TODO: use input range if available @@ -757,7 +757,7 @@ ConstantRange ConstantRange::castOp(Instruction::CastOps CastOp, SMin = SMin.sext(ResultBitWidth); SMax = SMax.sext(ResultBitWidth); } - return ConstantRange(std::move(SMin), std::move(SMax)); + return getNonEmpty(std::move(SMin), std::move(SMax) + 1); } case Instruction::FPTrunc: case Instruction::FPExt: diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 196aa50cf4060b..95d8ab95b2c097 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1658,40 +1658,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setMaxAtomicSizeInBitsSupported(128); if (Subtarget->isWindowsArm64EC()) { - // FIXME: are there other intrinsics we need to add here? - setLibcallName(RTLIB::MEMCPY, "#memcpy"); - setLibcallName(RTLIB::MEMSET, "#memset"); - setLibcallName(RTLIB::MEMMOVE, "#memmove"); - setLibcallName(RTLIB::REM_F32, "#fmodf"); - setLibcallName(RTLIB::REM_F64, "#fmod"); - setLibcallName(RTLIB::FMA_F32, "#fmaf"); - setLibcallName(RTLIB::FMA_F64, "#fma"); - setLibcallName(RTLIB::SQRT_F32, "#sqrtf"); - setLibcallName(RTLIB::SQRT_F64, "#sqrt"); - setLibcallName(RTLIB::CBRT_F32, "#cbrtf"); - setLibcallName(RTLIB::CBRT_F64, "#cbrt"); - setLibcallName(RTLIB::LOG_F32, "#logf"); - setLibcallName(RTLIB::LOG_F64, "#log"); - setLibcallName(RTLIB::LOG2_F32, "#log2f"); - setLibcallName(RTLIB::LOG2_F64, "#log2"); - setLibcallName(RTLIB::LOG10_F32, "#log10f"); - setLibcallName(RTLIB::LOG10_F64, "#log10"); - setLibcallName(RTLIB::EXP_F32, "#expf"); - setLibcallName(RTLIB::EXP_F64, "#exp"); - setLibcallName(RTLIB::EXP2_F32, "#exp2f"); - setLibcallName(RTLIB::EXP2_F64, "#exp2"); - setLibcallName(RTLIB::EXP10_F32, "#exp10f"); - setLibcallName(RTLIB::EXP10_F64, "#exp10"); - setLibcallName(RTLIB::SIN_F32, "#sinf"); - setLibcallName(RTLIB::SIN_F64, "#sin"); - setLibcallName(RTLIB::COS_F32, "#cosf"); - setLibcallName(RTLIB::COS_F64, "#cos"); - setLibcallName(RTLIB::POW_F32, "#powf"); - setLibcallName(RTLIB::POW_F64, "#pow"); - setLibcallName(RTLIB::LDEXP_F32, "#ldexpf"); - setLibcallName(RTLIB::LDEXP_F64, "#ldexp"); - setLibcallName(RTLIB::FREXP_F32, "#frexpf"); - setLibcallName(RTLIB::FREXP_F64, "#frexp"); + // FIXME: are there intrinsics we need to exclude from this? + for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { + auto code = static_cast(i); + auto libcallName = getLibcallName(code); + if ((libcallName != nullptr) && (libcallName[0] != '#')) { + setLibcallName(code, Saver.save(Twine("#") + libcallName).data()); + } + } } } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 541a810fb5cba0..74d0c4bde8dd2e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -1001,6 +1001,9 @@ class AArch64TargetLowering : public TargetLowering { /// make the right decision when generating code for different targets. const AArch64Subtarget *Subtarget; + llvm::BumpPtrAllocator BumpAlloc; + llvm::StringSaver Saver{BumpAlloc}; + bool isExtFreeImpl(const Instruction *Ext) const override; void addTypeForNEON(MVT VT); diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index 854563ab32bd8e..3ef04e488f016f 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -152,15 +152,15 @@ class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>; class LWPC_ENC : PCREL19_FM; -class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; -class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; +class MAX_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; +class MAX_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>; class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>; class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>; -class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; -class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; +class MINA_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; +class MINA_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>; class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>; diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp index c30129743a9626..2c2554b5b4bc3b 100644 --- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp +++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp @@ -388,32 +388,18 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword( Opcode = Mips::XOR; break; case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: - IsUnsigned = true; - IsMin = true; - break; case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: IsUnsigned = true; - IsMin = true; - break; + [[fallthrough]]; case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: - SEOp = Mips::SEB; - IsMin = true; - break; case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: IsMin = true; break; case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: - IsUnsigned = true; - IsMax = true; - break; case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: IsUnsigned = true; - IsMax = true; - break; + [[fallthrough]]; case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: - SEOp = Mips::SEB; - IsMax = true; - break; case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: IsMax = true; break; @@ -475,42 +461,14 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword( // For little endian we need to clear uninterested bits. if (STI->isLittle()) { - if (!IsUnsigned) { - BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal) - .addReg(OldVal) - .addReg(ShiftAmnt); - BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr) - .addReg(Incr) - .addReg(ShiftAmnt); - if (STI->hasMips32r2()) { - BuildMI(loopMBB, DL, TII->get(SEOp), OldVal).addReg(OldVal); - BuildMI(loopMBB, DL, TII->get(SEOp), Incr).addReg(Incr); - } else { - const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; - BuildMI(loopMBB, DL, TII->get(Mips::SLL), OldVal) - .addReg(OldVal, RegState::Kill) - .addImm(ShiftImm); - BuildMI(loopMBB, DL, TII->get(Mips::SRA), OldVal) - .addReg(OldVal, RegState::Kill) - .addImm(ShiftImm); - BuildMI(loopMBB, DL, TII->get(Mips::SLL), Incr) - .addReg(Incr, RegState::Kill) - .addImm(ShiftImm); - BuildMI(loopMBB, DL, TII->get(Mips::SRA), Incr) - .addReg(Incr, RegState::Kill) - .addImm(ShiftImm); - } - } else { - // and OldVal, OldVal, Mask - // and Incr, Incr, Mask - BuildMI(loopMBB, DL, TII->get(Mips::AND), OldVal) - .addReg(OldVal) - .addReg(Mask); - BuildMI(loopMBB, DL, TII->get(Mips::AND), Incr) - .addReg(Incr) - .addReg(Mask); - } + // and OldVal, OldVal, Mask + // and Incr, Incr, Mask + BuildMI(loopMBB, DL, TII->get(Mips::AND), OldVal) + .addReg(OldVal) + .addReg(Mask); + BuildMI(loopMBB, DL, TII->get(Mips::AND), Incr).addReg(Incr).addReg(Mask); } + // unsigned: sltu Scratch4, oldVal, Incr // signed: slt Scratch4, oldVal, Incr BuildMI(loopMBB, DL, TII->get(SLTScratch4), Scratch4) diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index 215a8ea8319046..6855471840e9db 100644 --- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -434,6 +434,50 @@ bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, default: // See if this is a generic print operand return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O); + case 'L': // Low order register of a twin word register operand + case 'H': // High order register of a twin word register operand + { + const SparcSubtarget &Subtarget = MF->getSubtarget(); + const MachineOperand &MO = MI->getOperand(OpNo); + const SparcRegisterInfo *RegisterInfo = Subtarget.getRegisterInfo(); + Register MOReg = MO.getReg(); + + Register HiReg, LoReg; + if (!SP::IntPairRegClass.contains(MOReg)) { + // If we aren't given a register pair already, find out which pair it + // belongs to. Note that here, the specified register operand, which + // refers to the high part of the twinword, needs to be an even-numbered + // register. + MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even, + &SP::IntPairRegClass); + if (!MOReg) { + SMLoc Loc; + OutContext.reportError( + Loc, "Hi part of pair should point to an even-numbered register"); + OutContext.reportError( + Loc, "(note that in some cases it might be necessary to manually " + "bind the input/output registers instead of relying on " + "automatic allocation)"); + return true; + } + } + + HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even); + LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd); + + Register Reg; + switch (ExtraCode[0]) { + case 'L': + Reg = LoReg; + break; + case 'H': + Reg = HiReg; + break; + } + + O << '%' << SparcInstPrinter::getRegisterName(Reg); + return false; + } case 'f': case 'r': break; diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 58ebe023cd61ec..7ce0aa22b99795 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -959,8 +959,10 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, SmallString<256> Code; unsigned MinSize = MI.getOperand(0).getImm(); - if (NextMI != MI.getParent()->end()) { + if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) { // Lower the next MachineInstr to find its byte size. + // If the next instruction is inline assembly, we skip lowering it for now, + // and assume we should always generate NOPs. MCInst MCI; MCIL.Lower(&*NextMI, MCI); diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 0a9e2c7f49f55f..1fbd69e38eaeec 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1)) TysForDecl.push_back( FixedVectorType::get(CI->getType(), E->Scalars.size())); + auto *CEI = cast(VL0); for (unsigned I : seq(0, CI->arg_size())) { ValueList OpVL; // Some intrinsics have scalar arguments. This argument should not be // vectorized. if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) { - CallInst *CEI = cast(VL0); ScalarArg = CEI->getArgOperand(I); OpVecs.push_back(CEI->getArgOperand(I)); if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I)) @@ -11671,6 +11671,25 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n"); return E->VectorizedValue; } + auto GetOperandSignedness = [&](unsigned Idx) { + const TreeEntry *OpE = getOperandEntry(E, Idx); + bool IsSigned = false; + auto It = MinBWs.find(OpE); + if (It != MinBWs.end()) + IsSigned = It->second.second; + else + IsSigned = any_of(OpE->Scalars, [&](Value *R) { + return !isKnownNonNegative(R, SimplifyQuery(*DL)); + }); + return IsSigned; + }; + ScalarArg = CEI->getArgOperand(I); + if (cast(OpVec->getType())->getElementType() != + ScalarArg->getType()) { + auto *CastTy = FixedVectorType::get(ScalarArg->getType(), + VecTy->getNumElements()); + OpVec = Builder.CreateIntCast(OpVec, CastTy, GetOperandSignedness(I)); + } LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n"); OpVecs.push_back(OpVec); if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I)) diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll index a96581bdb39a4c..f953c885ea7345 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll @@ -3,7 +3,6 @@ ; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 ; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM ; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 -; RUN: llc -march=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32 ; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL ; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 ; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL @@ -78,23 +77,6 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) { ; MMR6-NEXT: sync ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_max_32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: $BB0_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($4) -; MIPS32-NEXT: slt $3, $2, $5 -; MIPS32-NEXT: move $1, $2 -; MIPS32-NEXT: movn $1, $5, $3 -; MIPS32-NEXT: sc $1, 0($4) -; MIPS32-NEXT: beqz $1, $BB0_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_max_32: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: sync @@ -298,23 +280,6 @@ define i32 @test_min_32(ptr nocapture %ptr, i32 signext %val) { ; MMR6-NEXT: sync ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_min_32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: $BB1_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($4) -; MIPS32-NEXT: slt $3, $2, $5 -; MIPS32-NEXT: move $1, $2 -; MIPS32-NEXT: movz $1, $5, $3 -; MIPS32-NEXT: sc $1, 0($4) -; MIPS32-NEXT: beqz $1, $BB1_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_min_32: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: sync @@ -518,23 +483,6 @@ define i32 @test_umax_32(ptr nocapture %ptr, i32 signext %val) { ; MMR6-NEXT: sync ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_umax_32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: $BB2_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($4) -; MIPS32-NEXT: sltu $3, $2, $5 -; MIPS32-NEXT: move $1, $2 -; MIPS32-NEXT: movn $1, $5, $3 -; MIPS32-NEXT: sc $1, 0($4) -; MIPS32-NEXT: beqz $1, $BB2_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_umax_32: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: sync @@ -738,23 +686,6 @@ define i32 @test_umin_32(ptr nocapture %ptr, i32 signext %val) { ; MMR6-NEXT: sync ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_umin_32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: $BB3_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($4) -; MIPS32-NEXT: sltu $3, $2, $5 -; MIPS32-NEXT: move $1, $2 -; MIPS32-NEXT: movz $1, $5, $3 -; MIPS32-NEXT: sc $1, 0($4) -; MIPS32-NEXT: beqz $1, $BB3_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: sync -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_umin_32: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: sync @@ -1049,53 +980,6 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) { ; MMR6-NEXT: sync ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra -; -; MIPS32-LABEL: test_max_16: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 65535 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB4_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: srav $2, $2, $10 -; MIPS32-NEXT: srav $7, $7, $10 -; MIPS32-NEXT: sll $2, $2, 16 -; MIPS32-NEXT: sra $2, $2, 16 -; MIPS32-NEXT: sll $7, $7, 16 -; MIPS32-NEXT: sra $7, $7, 16 -; MIPS32-NEXT: slt $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movn $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB4_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 16 -; MIPS32-NEXT: sra $1, $1, 16 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop - ; ; MIPSEL-LABEL: test_max_16: ; MIPSEL: # %bb.0: # %entry @@ -1114,10 +998,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSEL-NEXT: $BB4_1: # %entry ; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSEL-NEXT: ll $2, 0($6) -; MIPSEL-NEXT: srav $2, $2, $10 -; MIPSEL-NEXT: srav $7, $7, $10 -; MIPSEL-NEXT: seh $2, $2 -; MIPSEL-NEXT: seh $7, $7 +; MIPSEL-NEXT: and $2, $2, $8 +; MIPSEL-NEXT: and $7, $7, $8 ; MIPSEL-NEXT: slt $5, $2, $7 ; MIPSEL-NEXT: move $3, $2 ; MIPSEL-NEXT: movn $3, $7, $5 @@ -1157,10 +1039,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSELR6-NEXT: $BB4_1: # %entry ; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT: ll $2, 0($6) -; MIPSELR6-NEXT: srav $2, $2, $10 -; MIPSELR6-NEXT: srav $7, $7, $10 -; MIPSELR6-NEXT: seh $2, $2 -; MIPSELR6-NEXT: seh $7, $7 +; MIPSELR6-NEXT: and $2, $2, $8 +; MIPSELR6-NEXT: and $7, $7, $8 ; MIPSELR6-NEXT: slt $5, $2, $7 ; MIPSELR6-NEXT: seleqz $3, $2, $5 ; MIPSELR6-NEXT: selnez $5, $7, $5 @@ -1199,10 +1079,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) { ; MMEL-NEXT: $BB4_1: # %entry ; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MMEL-NEXT: ll $2, 0($6) -; MMEL-NEXT: srav $2, $2, $10 -; MMEL-NEXT: srav $7, $7, $10 -; MMEL-NEXT: seh $2, $2 -; MMEL-NEXT: seh $7, $7 +; MMEL-NEXT: and $2, $2, $8 +; MMEL-NEXT: and $7, $7, $8 ; MMEL-NEXT: slt $5, $2, $7 ; MMEL-NEXT: or $3, $2, $zero ; MMEL-NEXT: movn $3, $7, $5 @@ -1240,10 +1118,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) { ; MMELR6-NEXT: $BB4_1: # %entry ; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MMELR6-NEXT: ll $2, 0($6) -; MMELR6-NEXT: srav $2, $2, $10 -; MMELR6-NEXT: srav $7, $7, $10 -; MMELR6-NEXT: seh $2, $2 -; MMELR6-NEXT: seh $7, $7 +; MMELR6-NEXT: and $2, $2, $8 +; MMELR6-NEXT: and $7, $7, $8 ; MMELR6-NEXT: slt $5, $2, $7 ; MMELR6-NEXT: seleqz $3, $2, $5 ; MMELR6-NEXT: selnez $5, $7, $5 @@ -1361,10 +1237,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) { ; MIPS64EL-NEXT: .LBB4_1: # %entry ; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64EL-NEXT: ll $2, 0($6) -; MIPS64EL-NEXT: srav $2, $2, $10 -; MIPS64EL-NEXT: srav $7, $7, $10 -; MIPS64EL-NEXT: seh $2, $2 -; MIPS64EL-NEXT: seh $7, $7 +; MIPS64EL-NEXT: and $2, $2, $8 +; MIPS64EL-NEXT: and $7, $7, $8 ; MIPS64EL-NEXT: slt $5, $2, $7 ; MIPS64EL-NEXT: move $3, $2 ; MIPS64EL-NEXT: movn $3, $7, $5 @@ -1404,10 +1278,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) { ; MIPS64ELR6-NEXT: .LBB4_1: # %entry ; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64ELR6-NEXT: ll $2, 0($6) -; MIPS64ELR6-NEXT: srav $2, $2, $10 -; MIPS64ELR6-NEXT: srav $7, $7, $10 -; MIPS64ELR6-NEXT: seh $2, $2 -; MIPS64ELR6-NEXT: seh $7, $7 +; MIPS64ELR6-NEXT: and $2, $2, $8 +; MIPS64ELR6-NEXT: and $7, $7, $8 ; MIPS64ELR6-NEXT: slt $5, $2, $7 ; MIPS64ELR6-NEXT: seleqz $3, $2, $5 ; MIPS64ELR6-NEXT: selnez $5, $7, $5 @@ -1590,52 +1462,6 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) { ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_min_16: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 65535 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB5_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: srav $2, $2, $10 -; MIPS32-NEXT: srav $7, $7, $10 -; MIPS32-NEXT: sll $2, $2, 16 -; MIPS32-NEXT: sra $2, $2, 16 -; MIPS32-NEXT: sll $7, $7, 16 -; MIPS32-NEXT: sra $7, $7, 16 -; MIPS32-NEXT: slt $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movz $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB5_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 16 -; MIPS32-NEXT: sra $1, $1, 16 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_min_16: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: addiu $sp, $sp, -8 @@ -1653,10 +1479,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSEL-NEXT: $BB5_1: # %entry ; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSEL-NEXT: ll $2, 0($6) -; MIPSEL-NEXT: srav $2, $2, $10 -; MIPSEL-NEXT: srav $7, $7, $10 -; MIPSEL-NEXT: seh $2, $2 -; MIPSEL-NEXT: seh $7, $7 +; MIPSEL-NEXT: and $2, $2, $8 +; MIPSEL-NEXT: and $7, $7, $8 ; MIPSEL-NEXT: slt $5, $2, $7 ; MIPSEL-NEXT: move $3, $2 ; MIPSEL-NEXT: movz $3, $7, $5 @@ -1696,10 +1520,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSELR6-NEXT: $BB5_1: # %entry ; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT: ll $2, 0($6) -; MIPSELR6-NEXT: srav $2, $2, $10 -; MIPSELR6-NEXT: srav $7, $7, $10 -; MIPSELR6-NEXT: seh $2, $2 -; MIPSELR6-NEXT: seh $7, $7 +; MIPSELR6-NEXT: and $2, $2, $8 +; MIPSELR6-NEXT: and $7, $7, $8 ; MIPSELR6-NEXT: slt $5, $2, $7 ; MIPSELR6-NEXT: selnez $3, $2, $5 ; MIPSELR6-NEXT: seleqz $5, $7, $5 @@ -1738,10 +1560,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) { ; MMEL-NEXT: $BB5_1: # %entry ; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MMEL-NEXT: ll $2, 0($6) -; MMEL-NEXT: srav $2, $2, $10 -; MMEL-NEXT: srav $7, $7, $10 -; MMEL-NEXT: seh $2, $2 -; MMEL-NEXT: seh $7, $7 +; MMEL-NEXT: and $2, $2, $8 +; MMEL-NEXT: and $7, $7, $8 ; MMEL-NEXT: slt $5, $2, $7 ; MMEL-NEXT: or $3, $2, $zero ; MMEL-NEXT: movz $3, $7, $5 @@ -1779,10 +1599,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) { ; MMELR6-NEXT: $BB5_1: # %entry ; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MMELR6-NEXT: ll $2, 0($6) -; MMELR6-NEXT: srav $2, $2, $10 -; MMELR6-NEXT: srav $7, $7, $10 -; MMELR6-NEXT: seh $2, $2 -; MMELR6-NEXT: seh $7, $7 +; MMELR6-NEXT: and $2, $2, $8 +; MMELR6-NEXT: and $7, $7, $8 ; MMELR6-NEXT: slt $5, $2, $7 ; MMELR6-NEXT: selnez $3, $2, $5 ; MMELR6-NEXT: seleqz $5, $7, $5 @@ -1900,10 +1718,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) { ; MIPS64EL-NEXT: .LBB5_1: # %entry ; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64EL-NEXT: ll $2, 0($6) -; MIPS64EL-NEXT: srav $2, $2, $10 -; MIPS64EL-NEXT: srav $7, $7, $10 -; MIPS64EL-NEXT: seh $2, $2 -; MIPS64EL-NEXT: seh $7, $7 +; MIPS64EL-NEXT: and $2, $2, $8 +; MIPS64EL-NEXT: and $7, $7, $8 ; MIPS64EL-NEXT: slt $5, $2, $7 ; MIPS64EL-NEXT: move $3, $2 ; MIPS64EL-NEXT: movz $3, $7, $5 @@ -1943,10 +1759,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) { ; MIPS64ELR6-NEXT: .LBB5_1: # %entry ; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64ELR6-NEXT: ll $2, 0($6) -; MIPS64ELR6-NEXT: srav $2, $2, $10 -; MIPS64ELR6-NEXT: srav $7, $7, $10 -; MIPS64ELR6-NEXT: seh $2, $2 -; MIPS64ELR6-NEXT: seh $7, $7 +; MIPS64ELR6-NEXT: and $2, $2, $8 +; MIPS64ELR6-NEXT: and $7, $7, $8 ; MIPS64ELR6-NEXT: slt $5, $2, $7 ; MIPS64ELR6-NEXT: selnez $3, $2, $5 ; MIPS64ELR6-NEXT: seleqz $5, $7, $5 @@ -2129,48 +1943,6 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) { ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_umax_16: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 65535 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB6_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: and $2, $2, $8 -; MIPS32-NEXT: and $7, $7, $8 -; MIPS32-NEXT: sltu $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movn $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB6_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 16 -; MIPS32-NEXT: sra $1, $1, 16 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_umax_16: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: addiu $sp, $sp, -8 @@ -2652,49 +2424,6 @@ define i16 @test_umin_16(ptr nocapture %ptr, i16 signext %val) { ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_umin_16: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 65535 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB7_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: and $2, $2, $8 -; MIPS32-NEXT: and $7, $7, $8 -; MIPS32-NEXT: sltu $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movz $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB7_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 16 -; MIPS32-NEXT: sra $1, $1, 16 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; -; ; MIPSEL-LABEL: test_umin_16: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: addiu $sp, $sp, -8 @@ -3051,7 +2780,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS-NEXT: # %bb.2: # %entry ; MIPS-NEXT: and $1, $2, $8 ; MIPS-NEXT: srlv $1, $1, $10 -; MIPS-NEXT: seb $1, $1 +; MIPS-NEXT: seh $1, $1 ; MIPS-NEXT: # %bb.3: # %entry ; MIPS-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS-NEXT: # %bb.4: # %entry @@ -3091,7 +2820,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSR6-NEXT: # %bb.2: # %entry ; MIPSR6-NEXT: and $1, $2, $8 ; MIPSR6-NEXT: srlv $1, $1, $10 -; MIPSR6-NEXT: seb $1, $1 +; MIPSR6-NEXT: seh $1, $1 ; MIPSR6-NEXT: # %bb.3: # %entry ; MIPSR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPSR6-NEXT: # %bb.4: # %entry @@ -3129,7 +2858,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MM-NEXT: # %bb.2: # %entry ; MM-NEXT: and $1, $2, $8 ; MM-NEXT: srlv $1, $1, $10 -; MM-NEXT: seb $1, $1 +; MM-NEXT: seh $1, $1 ; MM-NEXT: # %bb.3: # %entry ; MM-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MM-NEXT: # %bb.4: # %entry @@ -3168,7 +2897,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MMR6-NEXT: # %bb.2: # %entry ; MMR6-NEXT: and $1, $2, $8 ; MMR6-NEXT: srlv $1, $1, $10 -; MMR6-NEXT: seb $1, $1 +; MMR6-NEXT: seh $1, $1 ; MMR6-NEXT: # %bb.3: # %entry ; MMR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MMR6-NEXT: # %bb.4: # %entry @@ -3177,52 +2906,6 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_max_8: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB8_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: srav $2, $2, $10 -; MIPS32-NEXT: srav $7, $7, $10 -; MIPS32-NEXT: sll $2, $2, 24 -; MIPS32-NEXT: sra $2, $2, 24 -; MIPS32-NEXT: sll $7, $7, 24 -; MIPS32-NEXT: sra $7, $7, 24 -; MIPS32-NEXT: slt $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movn $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB8_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 24 -; MIPS32-NEXT: sra $1, $1, 24 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_max_8: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: addiu $sp, $sp, -8 @@ -3240,10 +2923,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSEL-NEXT: $BB8_1: # %entry ; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSEL-NEXT: ll $2, 0($6) -; MIPSEL-NEXT: srav $2, $2, $10 -; MIPSEL-NEXT: srav $7, $7, $10 -; MIPSEL-NEXT: seb $2, $2 -; MIPSEL-NEXT: seb $7, $7 +; MIPSEL-NEXT: and $2, $2, $8 +; MIPSEL-NEXT: and $7, $7, $8 ; MIPSEL-NEXT: slt $5, $2, $7 ; MIPSEL-NEXT: move $3, $2 ; MIPSEL-NEXT: movn $3, $7, $5 @@ -3256,7 +2937,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSEL-NEXT: # %bb.2: # %entry ; MIPSEL-NEXT: and $1, $2, $8 ; MIPSEL-NEXT: srlv $1, $1, $10 -; MIPSEL-NEXT: seb $1, $1 +; MIPSEL-NEXT: seh $1, $1 ; MIPSEL-NEXT: # %bb.3: # %entry ; MIPSEL-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPSEL-NEXT: # %bb.4: # %entry @@ -3283,10 +2964,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSELR6-NEXT: $BB8_1: # %entry ; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT: ll $2, 0($6) -; MIPSELR6-NEXT: srav $2, $2, $10 -; MIPSELR6-NEXT: srav $7, $7, $10 -; MIPSELR6-NEXT: seb $2, $2 -; MIPSELR6-NEXT: seb $7, $7 +; MIPSELR6-NEXT: and $2, $2, $8 +; MIPSELR6-NEXT: and $7, $7, $8 ; MIPSELR6-NEXT: slt $5, $2, $7 ; MIPSELR6-NEXT: seleqz $3, $2, $5 ; MIPSELR6-NEXT: selnez $5, $7, $5 @@ -3299,7 +2978,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSELR6-NEXT: # %bb.2: # %entry ; MIPSELR6-NEXT: and $1, $2, $8 ; MIPSELR6-NEXT: srlv $1, $1, $10 -; MIPSELR6-NEXT: seb $1, $1 +; MIPSELR6-NEXT: seh $1, $1 ; MIPSELR6-NEXT: # %bb.3: # %entry ; MIPSELR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPSELR6-NEXT: # %bb.4: # %entry @@ -3325,10 +3004,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MMEL-NEXT: $BB8_1: # %entry ; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MMEL-NEXT: ll $2, 0($6) -; MMEL-NEXT: srav $2, $2, $10 -; MMEL-NEXT: srav $7, $7, $10 -; MMEL-NEXT: seb $2, $2 -; MMEL-NEXT: seb $7, $7 +; MMEL-NEXT: and $2, $2, $8 +; MMEL-NEXT: and $7, $7, $8 ; MMEL-NEXT: slt $5, $2, $7 ; MMEL-NEXT: or $3, $2, $zero ; MMEL-NEXT: movn $3, $7, $5 @@ -3340,7 +3017,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MMEL-NEXT: # %bb.2: # %entry ; MMEL-NEXT: and $1, $2, $8 ; MMEL-NEXT: srlv $1, $1, $10 -; MMEL-NEXT: seb $1, $1 +; MMEL-NEXT: seh $1, $1 ; MMEL-NEXT: # %bb.3: # %entry ; MMEL-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MMEL-NEXT: # %bb.4: # %entry @@ -3366,10 +3043,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MMELR6-NEXT: $BB8_1: # %entry ; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MMELR6-NEXT: ll $2, 0($6) -; MMELR6-NEXT: srav $2, $2, $10 -; MMELR6-NEXT: srav $7, $7, $10 -; MMELR6-NEXT: seb $2, $2 -; MMELR6-NEXT: seb $7, $7 +; MMELR6-NEXT: and $2, $2, $8 +; MMELR6-NEXT: and $7, $7, $8 ; MMELR6-NEXT: slt $5, $2, $7 ; MMELR6-NEXT: seleqz $3, $2, $5 ; MMELR6-NEXT: selnez $5, $7, $5 @@ -3382,7 +3057,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MMELR6-NEXT: # %bb.2: # %entry ; MMELR6-NEXT: and $1, $2, $8 ; MMELR6-NEXT: srlv $1, $1, $10 -; MMELR6-NEXT: seb $1, $1 +; MMELR6-NEXT: seh $1, $1 ; MMELR6-NEXT: # %bb.3: # %entry ; MMELR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MMELR6-NEXT: # %bb.4: # %entry @@ -3421,7 +3096,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64-NEXT: # %bb.2: # %entry ; MIPS64-NEXT: and $1, $2, $8 ; MIPS64-NEXT: srlv $1, $1, $10 -; MIPS64-NEXT: seb $1, $1 +; MIPS64-NEXT: seh $1, $1 ; MIPS64-NEXT: # %bb.3: # %entry ; MIPS64-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64-NEXT: # %bb.4: # %entry @@ -3461,7 +3136,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64R6-NEXT: # %bb.2: # %entry ; MIPS64R6-NEXT: and $1, $2, $8 ; MIPS64R6-NEXT: srlv $1, $1, $10 -; MIPS64R6-NEXT: seb $1, $1 +; MIPS64R6-NEXT: seh $1, $1 ; MIPS64R6-NEXT: # %bb.3: # %entry ; MIPS64R6-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64R6-NEXT: # %bb.4: # %entry @@ -3487,10 +3162,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64EL-NEXT: .LBB8_1: # %entry ; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64EL-NEXT: ll $2, 0($6) -; MIPS64EL-NEXT: srav $2, $2, $10 -; MIPS64EL-NEXT: srav $7, $7, $10 -; MIPS64EL-NEXT: seb $2, $2 -; MIPS64EL-NEXT: seb $7, $7 +; MIPS64EL-NEXT: and $2, $2, $8 +; MIPS64EL-NEXT: and $7, $7, $8 ; MIPS64EL-NEXT: slt $5, $2, $7 ; MIPS64EL-NEXT: move $3, $2 ; MIPS64EL-NEXT: movn $3, $7, $5 @@ -3503,7 +3176,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64EL-NEXT: # %bb.2: # %entry ; MIPS64EL-NEXT: and $1, $2, $8 ; MIPS64EL-NEXT: srlv $1, $1, $10 -; MIPS64EL-NEXT: seb $1, $1 +; MIPS64EL-NEXT: seh $1, $1 ; MIPS64EL-NEXT: # %bb.3: # %entry ; MIPS64EL-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64EL-NEXT: # %bb.4: # %entry @@ -3530,10 +3203,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64ELR6-NEXT: .LBB8_1: # %entry ; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64ELR6-NEXT: ll $2, 0($6) -; MIPS64ELR6-NEXT: srav $2, $2, $10 -; MIPS64ELR6-NEXT: srav $7, $7, $10 -; MIPS64ELR6-NEXT: seb $2, $2 -; MIPS64ELR6-NEXT: seb $7, $7 +; MIPS64ELR6-NEXT: and $2, $2, $8 +; MIPS64ELR6-NEXT: and $7, $7, $8 ; MIPS64ELR6-NEXT: slt $5, $2, $7 ; MIPS64ELR6-NEXT: seleqz $3, $2, $5 ; MIPS64ELR6-NEXT: selnez $5, $7, $5 @@ -3546,7 +3217,7 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64ELR6-NEXT: # %bb.2: # %entry ; MIPS64ELR6-NEXT: and $1, $2, $8 ; MIPS64ELR6-NEXT: srlv $1, $1, $10 -; MIPS64ELR6-NEXT: seb $1, $1 +; MIPS64ELR6-NEXT: seh $1, $1 ; MIPS64ELR6-NEXT: # %bb.3: # %entry ; MIPS64ELR6-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64ELR6-NEXT: # %bb.4: # %entry @@ -3590,7 +3261,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS-NEXT: # %bb.2: # %entry ; MIPS-NEXT: and $1, $2, $8 ; MIPS-NEXT: srlv $1, $1, $10 -; MIPS-NEXT: seb $1, $1 +; MIPS-NEXT: seh $1, $1 ; MIPS-NEXT: # %bb.3: # %entry ; MIPS-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS-NEXT: # %bb.4: # %entry @@ -3630,7 +3301,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSR6-NEXT: # %bb.2: # %entry ; MIPSR6-NEXT: and $1, $2, $8 ; MIPSR6-NEXT: srlv $1, $1, $10 -; MIPSR6-NEXT: seb $1, $1 +; MIPSR6-NEXT: seh $1, $1 ; MIPSR6-NEXT: # %bb.3: # %entry ; MIPSR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPSR6-NEXT: # %bb.4: # %entry @@ -3668,7 +3339,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MM-NEXT: # %bb.2: # %entry ; MM-NEXT: and $1, $2, $8 ; MM-NEXT: srlv $1, $1, $10 -; MM-NEXT: seb $1, $1 +; MM-NEXT: seh $1, $1 ; MM-NEXT: # %bb.3: # %entry ; MM-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MM-NEXT: # %bb.4: # %entry @@ -3707,7 +3378,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MMR6-NEXT: # %bb.2: # %entry ; MMR6-NEXT: and $1, $2, $8 ; MMR6-NEXT: srlv $1, $1, $10 -; MMR6-NEXT: seb $1, $1 +; MMR6-NEXT: seh $1, $1 ; MMR6-NEXT: # %bb.3: # %entry ; MMR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MMR6-NEXT: # %bb.4: # %entry @@ -3716,52 +3387,6 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_min_8: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB9_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: srav $2, $2, $10 -; MIPS32-NEXT: srav $7, $7, $10 -; MIPS32-NEXT: sll $2, $2, 24 -; MIPS32-NEXT: sra $2, $2, 24 -; MIPS32-NEXT: sll $7, $7, 24 -; MIPS32-NEXT: sra $7, $7, 24 -; MIPS32-NEXT: slt $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movz $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB9_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 24 -; MIPS32-NEXT: sra $1, $1, 24 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_min_8: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: addiu $sp, $sp, -8 @@ -3779,10 +3404,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSEL-NEXT: $BB9_1: # %entry ; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSEL-NEXT: ll $2, 0($6) -; MIPSEL-NEXT: srav $2, $2, $10 -; MIPSEL-NEXT: srav $7, $7, $10 -; MIPSEL-NEXT: seb $2, $2 -; MIPSEL-NEXT: seb $7, $7 +; MIPSEL-NEXT: and $2, $2, $8 +; MIPSEL-NEXT: and $7, $7, $8 ; MIPSEL-NEXT: slt $5, $2, $7 ; MIPSEL-NEXT: move $3, $2 ; MIPSEL-NEXT: movz $3, $7, $5 @@ -3795,7 +3418,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSEL-NEXT: # %bb.2: # %entry ; MIPSEL-NEXT: and $1, $2, $8 ; MIPSEL-NEXT: srlv $1, $1, $10 -; MIPSEL-NEXT: seb $1, $1 +; MIPSEL-NEXT: seh $1, $1 ; MIPSEL-NEXT: # %bb.3: # %entry ; MIPSEL-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPSEL-NEXT: # %bb.4: # %entry @@ -3822,10 +3445,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSELR6-NEXT: $BB9_1: # %entry ; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT: ll $2, 0($6) -; MIPSELR6-NEXT: srav $2, $2, $10 -; MIPSELR6-NEXT: srav $7, $7, $10 -; MIPSELR6-NEXT: seb $2, $2 -; MIPSELR6-NEXT: seb $7, $7 +; MIPSELR6-NEXT: and $2, $2, $8 +; MIPSELR6-NEXT: and $7, $7, $8 ; MIPSELR6-NEXT: slt $5, $2, $7 ; MIPSELR6-NEXT: selnez $3, $2, $5 ; MIPSELR6-NEXT: seleqz $5, $7, $5 @@ -3838,7 +3459,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPSELR6-NEXT: # %bb.2: # %entry ; MIPSELR6-NEXT: and $1, $2, $8 ; MIPSELR6-NEXT: srlv $1, $1, $10 -; MIPSELR6-NEXT: seb $1, $1 +; MIPSELR6-NEXT: seh $1, $1 ; MIPSELR6-NEXT: # %bb.3: # %entry ; MIPSELR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPSELR6-NEXT: # %bb.4: # %entry @@ -3864,10 +3485,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MMEL-NEXT: $BB9_1: # %entry ; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ; MMEL-NEXT: ll $2, 0($6) -; MMEL-NEXT: srav $2, $2, $10 -; MMEL-NEXT: srav $7, $7, $10 -; MMEL-NEXT: seb $2, $2 -; MMEL-NEXT: seb $7, $7 +; MMEL-NEXT: and $2, $2, $8 +; MMEL-NEXT: and $7, $7, $8 ; MMEL-NEXT: slt $5, $2, $7 ; MMEL-NEXT: or $3, $2, $zero ; MMEL-NEXT: movz $3, $7, $5 @@ -3879,7 +3498,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MMEL-NEXT: # %bb.2: # %entry ; MMEL-NEXT: and $1, $2, $8 ; MMEL-NEXT: srlv $1, $1, $10 -; MMEL-NEXT: seb $1, $1 +; MMEL-NEXT: seh $1, $1 ; MMEL-NEXT: # %bb.3: # %entry ; MMEL-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MMEL-NEXT: # %bb.4: # %entry @@ -3905,10 +3524,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MMELR6-NEXT: $BB9_1: # %entry ; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MMELR6-NEXT: ll $2, 0($6) -; MMELR6-NEXT: srav $2, $2, $10 -; MMELR6-NEXT: srav $7, $7, $10 -; MMELR6-NEXT: seb $2, $2 -; MMELR6-NEXT: seb $7, $7 +; MMELR6-NEXT: and $2, $2, $8 +; MMELR6-NEXT: and $7, $7, $8 ; MMELR6-NEXT: slt $5, $2, $7 ; MMELR6-NEXT: selnez $3, $2, $5 ; MMELR6-NEXT: seleqz $5, $7, $5 @@ -3921,7 +3538,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MMELR6-NEXT: # %bb.2: # %entry ; MMELR6-NEXT: and $1, $2, $8 ; MMELR6-NEXT: srlv $1, $1, $10 -; MMELR6-NEXT: seb $1, $1 +; MMELR6-NEXT: seh $1, $1 ; MMELR6-NEXT: # %bb.3: # %entry ; MMELR6-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MMELR6-NEXT: # %bb.4: # %entry @@ -3960,7 +3577,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64-NEXT: # %bb.2: # %entry ; MIPS64-NEXT: and $1, $2, $8 ; MIPS64-NEXT: srlv $1, $1, $10 -; MIPS64-NEXT: seb $1, $1 +; MIPS64-NEXT: seh $1, $1 ; MIPS64-NEXT: # %bb.3: # %entry ; MIPS64-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64-NEXT: # %bb.4: # %entry @@ -4000,7 +3617,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64R6-NEXT: # %bb.2: # %entry ; MIPS64R6-NEXT: and $1, $2, $8 ; MIPS64R6-NEXT: srlv $1, $1, $10 -; MIPS64R6-NEXT: seb $1, $1 +; MIPS64R6-NEXT: seh $1, $1 ; MIPS64R6-NEXT: # %bb.3: # %entry ; MIPS64R6-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64R6-NEXT: # %bb.4: # %entry @@ -4026,10 +3643,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64EL-NEXT: .LBB9_1: # %entry ; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64EL-NEXT: ll $2, 0($6) -; MIPS64EL-NEXT: srav $2, $2, $10 -; MIPS64EL-NEXT: srav $7, $7, $10 -; MIPS64EL-NEXT: seb $2, $2 -; MIPS64EL-NEXT: seb $7, $7 +; MIPS64EL-NEXT: and $2, $2, $8 +; MIPS64EL-NEXT: and $7, $7, $8 ; MIPS64EL-NEXT: slt $5, $2, $7 ; MIPS64EL-NEXT: move $3, $2 ; MIPS64EL-NEXT: movz $3, $7, $5 @@ -4042,7 +3657,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64EL-NEXT: # %bb.2: # %entry ; MIPS64EL-NEXT: and $1, $2, $8 ; MIPS64EL-NEXT: srlv $1, $1, $10 -; MIPS64EL-NEXT: seb $1, $1 +; MIPS64EL-NEXT: seh $1, $1 ; MIPS64EL-NEXT: # %bb.3: # %entry ; MIPS64EL-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64EL-NEXT: # %bb.4: # %entry @@ -4069,10 +3684,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64ELR6-NEXT: .LBB9_1: # %entry ; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS64ELR6-NEXT: ll $2, 0($6) -; MIPS64ELR6-NEXT: srav $2, $2, $10 -; MIPS64ELR6-NEXT: srav $7, $7, $10 -; MIPS64ELR6-NEXT: seb $2, $2 -; MIPS64ELR6-NEXT: seb $7, $7 +; MIPS64ELR6-NEXT: and $2, $2, $8 +; MIPS64ELR6-NEXT: and $7, $7, $8 ; MIPS64ELR6-NEXT: slt $5, $2, $7 ; MIPS64ELR6-NEXT: selnez $3, $2, $5 ; MIPS64ELR6-NEXT: seleqz $5, $7, $5 @@ -4085,7 +3698,7 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS64ELR6-NEXT: # %bb.2: # %entry ; MIPS64ELR6-NEXT: and $1, $2, $8 ; MIPS64ELR6-NEXT: srlv $1, $1, $10 -; MIPS64ELR6-NEXT: seb $1, $1 +; MIPS64ELR6-NEXT: seh $1, $1 ; MIPS64ELR6-NEXT: # %bb.3: # %entry ; MIPS64ELR6-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64ELR6-NEXT: # %bb.4: # %entry @@ -4255,48 +3868,6 @@ define i8 @test_umax_8(ptr nocapture %ptr, i8 signext %val) { ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_umax_8: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB10_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: and $2, $2, $8 -; MIPS32-NEXT: and $7, $7, $8 -; MIPS32-NEXT: sltu $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movn $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB10_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 16 -; MIPS32-NEXT: sra $1, $1, 16 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_umax_8: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: addiu $sp, $sp, -8 @@ -4778,48 +4349,6 @@ define i8 @test_umin_8(ptr nocapture %ptr, i8 signext %val) { ; MMR6-NEXT: addiu $sp, $sp, 8 ; MMR6-NEXT: jrc $ra ; -; MIPS32-LABEL: test_umin_8: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -8 -; MIPS32-NEXT: .cfi_def_cfa_offset 8 -; MIPS32-NEXT: # kill: def $at killed $a1 -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $1, $zero, -4 -; MIPS32-NEXT: and $6, $4, $1 -; MIPS32-NEXT: andi $1, $4, 3 -; MIPS32-NEXT: sll $10, $1, 3 -; MIPS32-NEXT: ori $1, $zero, 255 -; MIPS32-NEXT: sllv $8, $1, $10 -; MIPS32-NEXT: nor $9, $zero, $8 -; MIPS32-NEXT: sllv $7, $5, $10 -; MIPS32-NEXT: $BB11_1: # %entry -; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $2, 0($6) -; MIPS32-NEXT: and $2, $2, $8 -; MIPS32-NEXT: and $7, $7, $8 -; MIPS32-NEXT: sltu $5, $2, $7 -; MIPS32-NEXT: move $3, $2 -; MIPS32-NEXT: movz $3, $7, $5 -; MIPS32-NEXT: and $3, $3, $8 -; MIPS32-NEXT: and $4, $2, $9 -; MIPS32-NEXT: or $4, $4, $3 -; MIPS32-NEXT: sc $4, 0($6) -; MIPS32-NEXT: beqz $4, $BB11_1 -; MIPS32-NEXT: nop -; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $1, $2, $8 -; MIPS32-NEXT: srlv $1, $1, $10 -; MIPS32-NEXT: sll $1, $1, 16 -; MIPS32-NEXT: sra $1, $1, 16 -; MIPS32-NEXT: # %bb.3: # %entry -; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill -; MIPS32-NEXT: # %bb.4: # %entry -; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload -; MIPS32-NEXT: sync -; MIPS32-NEXT: addiu $sp, $sp, 8 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop -; ; MIPSEL-LABEL: test_umin_8: ; MIPSEL: # %bb.0: # %entry ; MIPSEL-NEXT: addiu $sp, $sp, -8 diff --git a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll index 5bf2adbeb75c95..07eb67df6e5f7e 100644 --- a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll +++ b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll @@ -11,3 +11,12 @@ entry: tail call void asm sideeffect "faddq $0,$1,$2", "{f38},{f0},{f0}"(fp128 0xL0, fp128 0xL0, fp128 0xL0) ret void } + +; CHECK-label:test_twinword_error +; CHECK: error: Hi part of pair should point to an even-numbered register +; CHECK: error: (note that in some cases it might be necessary to manually bind the input/output registers instead of relying on automatic allocation) + +define i64 @test_twinword_error(){ + %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i1}"() + ret i64 %1 +} diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll index 8bf34bf1609c18..efb7f7c15220c2 100644 --- a/llvm/test/CodeGen/SPARC/inlineasm.ll +++ b/llvm/test/CodeGen/SPARC/inlineasm.ll @@ -143,3 +143,12 @@ entry: %1 = call double asm sideeffect "faddd $1, $2, $0", "=f,f,e"(i64 0, i64 0) ret void } + +; CHECK-label:test_twinword +; CHECK: rd %asr5, %i1 +; CHECK: srlx %i1, 32, %i0 + +define i64 @test_twinword(){ + %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i0}"() + ret i64 %1 +} diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll index 3fc4ed99fad0fa..f8d32fc2d29252 100644 --- a/llvm/test/CodeGen/X86/addcarry.ll +++ b/llvm/test/CodeGen/X86/addcarry.ll @@ -1490,3 +1490,26 @@ define { i64, i64 } @addcarry_commutative_2(i64 %x0, i64 %x1, i64 %y0, i64 %y1) %r1 = insertvalue { i64, i64 } %r0, i64 %b1s, 1 ret { i64, i64 } %r1 } + +define i1 @pr84831(i64 %arg) { +; CHECK-LABEL: pr84831: +; CHECK: # %bb.0: +; CHECK-NEXT: testq %rdi, %rdi +; CHECK-NEXT: setne %al +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: addb $-1, %al +; CHECK-NEXT: adcq $1, %rcx +; CHECK-NEXT: setb %al +; CHECK-NEXT: retq + %a = icmp ult i64 0, %arg + %add1 = add i64 0, 1 + %carryout1 = icmp ult i64 %add1, 0 + %b = zext i1 %a to i64 + %add2 = add i64 %add1, %b + %carryout2 = icmp ult i64 %add2, %add1 + %zc1 = zext i1 %carryout1 to i63 + %zc2 = zext i1 %carryout2 to i63 + %or = or i63 %zc1, %zc2 + %trunc = trunc i63 %or to i1 + ret i1 %trunc +} diff --git a/llvm/test/CodeGen/X86/patchable-prologue.ll b/llvm/test/CodeGen/X86/patchable-prologue.ll index 71a392845fdea3..43761e3d1e1eb9 100644 --- a/llvm/test/CodeGen/X86/patchable-prologue.ll +++ b/llvm/test/CodeGen/X86/patchable-prologue.ll @@ -193,3 +193,20 @@ do.body: ; preds = %do.body, %entry do.end: ; preds = %do.body ret void } + + +; Test that inline asm is properly hotpatched. We currently don't examine the +; asm instruction when printing it, thus we always emit patching NOPs. + +; 64: inline_asm: +; 64-NEXT: # %bb.0: +; 64-NEXT: xchgw %ax, %ax # encoding: [0x66,0x90] +; 64-NEXT: #APP +; 64-NEXT: int3 # encoding: [0xcc] +; 64-NEXT: #NO_APP + +define dso_local void @inline_asm() "patchable-function"="prologue-short-redirect" { +entry: + call void asm sideeffect "int3", "~{dirflag},~{fpsr},~{flags}"() + ret void +} diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt index 1a73178a1f6a7e..d6f10e96d4769f 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt @@ -116,14 +116,14 @@ 0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2 0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4 0x37 0x10 0x64 0x00 # CHECK: selnez $2, $3, $4 -0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4 -0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4 +0x1d 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4 +0x1d 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4 +0x1e 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4 +0x1e 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4 -0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4 -0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4 0x14 0x10 0x04 0x46 # CHECK: seleqz.s $f0, $f2, $f4 0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt index 53ea0258e1c4bc..e1ba009f3c4c8c 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt @@ -92,8 +92,8 @@ 0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 -0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 -0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1d # CHECK: mina.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: max.s $f0, $f2, $f4 0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 @@ -103,8 +103,8 @@ 0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 -0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 -0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: mina.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: max.d $f0, $f2, $f4 0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt index 9aeea45472aebb..a7dfbd209b4e48 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt @@ -140,15 +140,15 @@ 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268 0x98 0x18 0x24 0x46 # CHECK: maddf.d $f2, $f3, $f4 0x98 0x18 0x04 0x46 # CHECK: maddf.s $f2, $f3, $f4 -0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4 -0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4 +0x1e 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4 +0x1e 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4 0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4 -0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4 -0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4 +0x1d 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4 +0x1d 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4 0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index 32b91c6c6842e1..0030e51d6c2387 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -111,8 +111,8 @@ 0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 -0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 -0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1d # CHECK: mina.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: max.s $f0, $f2, $f4 0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 @@ -122,8 +122,8 @@ 0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 -0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 -0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: mina.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: max.d $f0, $f2, $f4 0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s index 0f098a176a67cc..0d705b6f242615 100644 --- a/llvm/test/MC/Mips/mips32r6/valid.s +++ b/llvm/test/MC/Mips/mips32r6/valid.s @@ -170,14 +170,14 @@ a: sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] - max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] - max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] - mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] - mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s index c50bd9e31c232e..ff6e1d73fbeb48 100644 --- a/llvm/test/MC/Mips/mips64r6/valid.s +++ b/llvm/test/MC/Mips/mips64r6/valid.s @@ -183,14 +183,14 @@ a: lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98] maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98] - max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] - max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] - mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] - mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] diff --git a/llvm/test/Transforms/Float2Int/pr79158.ll b/llvm/test/Transforms/Float2Int/pr79158.ll new file mode 100644 index 00000000000000..5e78cc0bc66fdb --- /dev/null +++ b/llvm/test/Transforms/Float2Int/pr79158.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=float2int -S | FileCheck %s + +define i32 @pr79158(i32 %x) { +; CHECK-LABEL: define i32 @pr79158( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], 0 +; CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[CMP]] to i64 +; CHECK-NEXT: [[MUL1:%.*]] = mul i64 [[TMP0]], 4294967295 +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[MUL1]] to i32 +; CHECK-NEXT: ret i32 [[TMP1]] +; +entry: + %cmp = icmp sgt i32 %x, 0 + %conv = uitofp i1 %cmp to double + %mul = fmul double %conv, 0x41EFFFFFFFE00000 + %conv1 = fptoui double %mul to i32 + ret i32 %conv1 +} diff --git a/llvm/test/Transforms/InstSimplify/pr87042.ll b/llvm/test/Transforms/InstSimplify/pr87042.ll new file mode 100644 index 00000000000000..800d27c9e65043 --- /dev/null +++ b/llvm/test/Transforms/InstSimplify/pr87042.ll @@ -0,0 +1,42 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=instsimplify -S | FileCheck %s + +; %or2 cannot be folded into %or1 because %or1 has disjoint. +; TODO: Can we move the logic into InstCombine and drop the disjoint flag? +define i64 @test(i1 %cond, i64 %x) { +; CHECK-LABEL: define i64 @test( +; CHECK-SAME: i1 [[COND:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[OR1:%.*]] = or disjoint i64 [[X]], 7 +; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND]], i64 [[OR1]], i64 [[X]] +; CHECK-NEXT: [[OR2:%.*]] = or i64 [[SEL1]], 7 +; CHECK-NEXT: ret i64 [[OR2]] +; + %or1 = or disjoint i64 %x, 7 + %sel1 = select i1 %cond, i64 %or1, i64 %x + %or2 = or i64 %sel1, 7 + ret i64 %or2 +} + +define i64 @pr87042(i64 %x) { +; CHECK-LABEL: define i64 @pr87042( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[AND1:%.*]] = and i64 [[X]], 65535 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[AND1]], 0 +; CHECK-NEXT: [[OR1:%.*]] = or disjoint i64 [[X]], 7 +; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i64 [[OR1]], i64 [[X]] +; CHECK-NEXT: [[AND2:%.*]] = and i64 [[SEL1]], 16776960 +; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 [[AND2]], 0 +; CHECK-NEXT: [[OR2:%.*]] = or i64 [[SEL1]], 7 +; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i64 [[OR2]], i64 [[SEL1]] +; CHECK-NEXT: ret i64 [[SEL2]] +; + %and1 = and i64 %x, 65535 + %cmp1 = icmp eq i64 %and1, 0 + %or1 = or disjoint i64 %x, 7 + %sel1 = select i1 %cmp1, i64 %or1, i64 %x + %and2 = and i64 %sel1, 16776960 + %cmp2 = icmp eq i64 %and2, 0 + %or2 = or i64 %sel1, 7 + %sel2 = select i1 %cmp2, i64 %or2, i64 %sel1 + ret i64 %sel2 +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll new file mode 100644 index 00000000000000..49e89feb475b95 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll @@ -0,0 +1,82 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-pc-windows-msvc19.34.0 < %s | FileCheck %s + +define void @test(ptr %0, i8 %1, i1 %cmp12.i) { +; CHECK-LABEL: define void @test( +; CHECK-SAME: ptr [[TMP0:%.*]], i8 [[TMP1:%.*]], i1 [[CMP12_I:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i1> poison, i1 [[CMP12_I]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <8 x i32> zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> poison, i8 [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> poison, <8 x i32> zeroinitializer +; CHECK-NEXT: br label [[PRE:%.*]] +; CHECK: pre: +; CHECK-NEXT: [[TMP6:%.*]] = zext <8 x i8> [[TMP5]] to <8 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i32> @llvm.umax.v8i32(<8 x i32> [[TMP6]], <8 x i32> ) +; CHECK-NEXT: [[TMP8:%.*]] = add <8 x i32> [[TMP7]], +; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[TMP8]], <8 x i32> [[TMP6]] +; CHECK-NEXT: [[TMP10:%.*]] = trunc <8 x i32> [[TMP9]] to <8 x i8> +; CHECK-NEXT: store <8 x i8> [[TMP10]], ptr [[TMP0]], align 1 +; CHECK-NEXT: br label [[PRE]] +; +entry: + %idx11 = getelementptr i8, ptr %0, i64 1 + %idx22 = getelementptr i8, ptr %0, i64 2 + %idx33 = getelementptr i8, ptr %0, i64 3 + %idx44 = getelementptr i8, ptr %0, i64 4 + %idx55 = getelementptr i8, ptr %0, i64 5 + %idx66 = getelementptr i8, ptr %0, i64 6 + %idx77 = getelementptr i8, ptr %0, i64 7 + br label %pre + +pre: + %conv.i = zext i8 %1 to i32 + %2 = tail call i32 @llvm.umax.i32(i32 %conv.i, i32 1) + %.sroa.speculated.i = add i32 %2, 1 + %intensity.0.i = select i1 %cmp12.i, i32 %.sroa.speculated.i, i32 %conv.i + %conv14.i = trunc i32 %intensity.0.i to i8 + store i8 %conv14.i, ptr %0, align 1 + %conv.i.1 = zext i8 %1 to i32 + %3 = tail call i32 @llvm.umax.i32(i32 %conv.i.1, i32 1) + %ss1 = add i32 %3, 1 + %ii1 = select i1 %cmp12.i, i32 %ss1, i32 %conv.i.1 + %conv14.i.1 = trunc i32 %ii1 to i8 + store i8 %conv14.i.1, ptr %idx11, align 1 + %conv.i.2 = zext i8 %1 to i32 + %4 = tail call i32 @llvm.umax.i32(i32 %conv.i.2, i32 1) + %ss2 = add i32 %4, 1 + %ii2 = select i1 %cmp12.i, i32 %ss2, i32 %conv.i.2 + %conv14.i.2 = trunc i32 %ii2 to i8 + store i8 %conv14.i.2, ptr %idx22, align 1 + %conv.i.3 = zext i8 %1 to i32 + %5 = tail call i32 @llvm.umax.i32(i32 %conv.i.3, i32 1) + %ss3 = add i32 %5, 1 + %ii3 = select i1 %cmp12.i, i32 %ss3, i32 %conv.i.3 + %conv14.i.3 = trunc i32 %ii3 to i8 + store i8 %conv14.i.3, ptr %idx33, align 1 + %conv.i.4 = zext i8 %1 to i32 + %6 = tail call i32 @llvm.umax.i32(i32 %conv.i.4, i32 1) + %ss4 = add i32 %6, 1 + %ii4 = select i1 %cmp12.i, i32 %ss4, i32 %conv.i.4 + %conv14.i.4 = trunc i32 %ii4 to i8 + store i8 %conv14.i.4, ptr %idx44, align 1 + %conv.i.5 = zext i8 %1 to i32 + %7 = tail call i32 @llvm.umax.i32(i32 %conv.i.5, i32 1) + %ss5 = add i32 %7, 1 + %ii5 = select i1 %cmp12.i, i32 %ss5, i32 %conv.i.5 + %conv14.i.5 = trunc i32 %ii5 to i8 + store i8 %conv14.i.5, ptr %idx55, align 1 + %conv.i.6 = zext i8 %1 to i32 + %8 = tail call i32 @llvm.umax.i32(i32 %conv.i.6, i32 1) + %ss6 = add i32 %8, 1 + %ii6 = select i1 %cmp12.i, i32 %ss6, i32 %conv.i.6 + %conv14.i.6 = trunc i32 %ii6 to i8 + store i8 %conv14.i.6, ptr %idx66, align 1 + %conv.i.7 = zext i8 %1 to i32 + %9 = tail call i32 @llvm.umax.i32(i32 %conv.i.7, i32 1) + %ss7 = add i32 %9, 1 + %ii7 = select i1 %cmp12.i, i32 %ss7, i32 %conv.i.7 + %conv14.i.7 = trunc i32 %ii7 to i8 + store i8 %conv14.i.7, ptr %idx77, align 1 + br label %pre +} diff --git a/llvm/unittests/IR/ConstantRangeTest.cpp b/llvm/unittests/IR/ConstantRangeTest.cpp index e505af5d3275ef..f60bb4c135bec3 100644 --- a/llvm/unittests/IR/ConstantRangeTest.cpp +++ b/llvm/unittests/IR/ConstantRangeTest.cpp @@ -2479,6 +2479,24 @@ TEST_F(ConstantRangeTest, castOps) { ConstantRange IntToPtr = A.castOp(Instruction::IntToPtr, 64); EXPECT_EQ(64u, IntToPtr.getBitWidth()); EXPECT_TRUE(IntToPtr.isFullSet()); + + ConstantRange UIToFP = A.castOp(Instruction::UIToFP, 16); + EXPECT_EQ(16u, UIToFP.getBitWidth()); + EXPECT_TRUE(UIToFP.isFullSet()); + + ConstantRange UIToFP2 = A.castOp(Instruction::UIToFP, 64); + ConstantRange B(APInt(64, 0), APInt(64, 65536)); + EXPECT_EQ(64u, UIToFP2.getBitWidth()); + EXPECT_EQ(B, UIToFP2); + + ConstantRange SIToFP = A.castOp(Instruction::SIToFP, 16); + EXPECT_EQ(16u, SIToFP.getBitWidth()); + EXPECT_TRUE(SIToFP.isFullSet()); + + ConstantRange SIToFP2 = A.castOp(Instruction::SIToFP, 64); + ConstantRange C(APInt(64, -32768), APInt(64, 32768)); + EXPECT_EQ(64u, SIToFP2.getBitWidth()); + EXPECT_EQ(C, SIToFP2); } TEST_F(ConstantRangeTest, binaryAnd) { diff --git a/llvm/utils/lit/lit/__init__.py b/llvm/utils/lit/lit/__init__.py index 9165056a56bd4d..fcf4a9d8b5f398 100644 --- a/llvm/utils/lit/lit/__init__.py +++ b/llvm/utils/lit/lit/__init__.py @@ -2,7 +2,7 @@ __author__ = "Daniel Dunbar" __email__ = "daniel@minormatter.com" -__versioninfo__ = (18, 1, 3) +__versioninfo__ = (18, 1, 4) __version__ = ".".join(str(v) for v in __versioninfo__) + "dev" __all__ = [] diff --git a/llvm/utils/release/github-upload-release.py b/llvm/utils/release/github-upload-release.py index 14ec05062d88c8..8343dee937f78f 100755 --- a/llvm/utils/release/github-upload-release.py +++ b/llvm/utils/release/github-upload-release.py @@ -107,6 +107,6 @@ def upload_files(repo, release, files): sys.exit(1) if args.command == "create": - create_release(llvm_repo, args.release, args.user) + create_release(llvm_repo, args.release) if args.command == "upload": upload_files(llvm_repo, args.release, args.files) diff --git a/polly/lib/Exchange/JSONExporter.cpp b/polly/lib/Exchange/JSONExporter.cpp index 74d4e6c7993fa3..63fb06a634cc12 100644 --- a/polly/lib/Exchange/JSONExporter.cpp +++ b/polly/lib/Exchange/JSONExporter.cpp @@ -842,7 +842,7 @@ class JSONImporterPrinterLegacyPass final : public ScopPass { public: static char ID; - JSONImporterPrinterLegacyPass() : JSONImporterPrinterLegacyPass(outs()){}; + JSONImporterPrinterLegacyPass() : JSONImporterPrinterLegacyPass(outs()) {} explicit JSONImporterPrinterLegacyPass(llvm::raw_ostream &OS) : ScopPass(ID), OS(OS) {} diff --git a/polly/lib/Transform/DeLICM.cpp b/polly/lib/Transform/DeLICM.cpp index 51e701346563a1..dae5e79639f7be 100644 --- a/polly/lib/Transform/DeLICM.cpp +++ b/polly/lib/Transform/DeLICM.cpp @@ -1463,7 +1463,7 @@ class DeLICMPrinterLegacyPass final : public ScopPass { public: static char ID; - DeLICMPrinterLegacyPass() : DeLICMPrinterLegacyPass(outs()){}; + DeLICMPrinterLegacyPass() : DeLICMPrinterLegacyPass(outs()) {} explicit DeLICMPrinterLegacyPass(llvm::raw_ostream &OS) : ScopPass(ID), OS(OS) {} diff --git a/polly/lib/Transform/FlattenSchedule.cpp b/polly/lib/Transform/FlattenSchedule.cpp index 53e230be7a6945..87bf642ba0d92b 100644 --- a/polly/lib/Transform/FlattenSchedule.cpp +++ b/polly/lib/Transform/FlattenSchedule.cpp @@ -103,7 +103,7 @@ class FlattenSchedulePrinterLegacyPass final : public ScopPass { static char ID; FlattenSchedulePrinterLegacyPass() - : FlattenSchedulePrinterLegacyPass(outs()){}; + : FlattenSchedulePrinterLegacyPass(outs()) {} explicit FlattenSchedulePrinterLegacyPass(llvm::raw_ostream &OS) : ScopPass(ID), OS(OS) {} diff --git a/polly/lib/Transform/ForwardOpTree.cpp b/polly/lib/Transform/ForwardOpTree.cpp index 2bed3e35412d76..5e6de2e182a526 100644 --- a/polly/lib/Transform/ForwardOpTree.cpp +++ b/polly/lib/Transform/ForwardOpTree.cpp @@ -1149,7 +1149,7 @@ class ForwardOpTreePrinterLegacyPass final : public ScopPass { public: static char ID; - ForwardOpTreePrinterLegacyPass() : ForwardOpTreePrinterLegacyPass(outs()){}; + ForwardOpTreePrinterLegacyPass() : ForwardOpTreePrinterLegacyPass(outs()) {} explicit ForwardOpTreePrinterLegacyPass(llvm::raw_ostream &OS) : ScopPass(ID), OS(OS) {}