Add 'pythondata_cpu_mor1kx/verilog/' from commit '06e2e46afbad62572c3…

…1bde88e8f2424e23ecda2' git-subtree-dir: pythondata_cpu_mor1kx/verilog git-subtree-mainline: 3556c91 git-subtree-split: 06e2e46
litex-hub · Apr 9, 2020 · db3cd95 · db3cd95
2 parents 3556c91 + 06e2e46
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diff --git a/pythondata_cpu_mor1kx/verilog/.gitignore b/pythondata_cpu_mor1kx/verilog/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/pythondata_cpu_mor1kx/verilog/.travis.yml b/pythondata_cpu_mor1kx/verilog/.travis.yml
@@ -0,0 +1,42 @@
+language: c
+cache: ccache
+sudo: true
+dist: trusty
+
+services:
+  - docker
+
+before_install:
+  -  docker pull librecores/librecores-ci-openrisc
+  -  docker images
+
+script:
+  - docker run --rm -v $(pwd):/src -e "JOB=$JOB" -e "SIM=$SIM" -e "PIPELINE=$PIPELINE" -e "EXPECTED_FAILURES=$EXPECTED_FAILURES" -e "EXTRA_CORE_ARGS=$EXTRA_CORE_ARGS" librecores/librecores-ci-openrisc /src/.travis/test.sh
+
+matrix:
+  fast_finish: true
+
+jobs:
+  allow_failures:
+    - env: JOB=or1k-tests SIM=icarus PIPELINE=ESPRESSO
+  include:
+    - stage: verilator
+      env: JOB=verilator
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy" EXTRA_CORE_ARGS="--feature_dmmu NONE"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy or1k-dsxinsn" EXTRA_CORE_ARGS="--feature_immu NONE"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy" EXTRA_CORE_ARGS="--feature_datacache NONE"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy" EXTRA_CORE_ARGS="--feature_instructioncache NONE"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy" EXTRA_CORE_ARGS="--feature_debugunit NONE"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy or1k-cmov" EXTRA_CORE_ARGS="--feature_cmov NONE"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=CAPPUCCINO EXPECTED_FAILURES="or1k-cy or1k-ext" EXTRA_CORE_ARGS="--feature_ext NONE"
+    - stage: testing
+      env: JOB=or1k-tests SIM=icarus PIPELINE=ESPRESSO
diff --git a/pythondata_cpu_mor1kx/verilog/.travis/run-or1k-tests.sh b/pythondata_cpu_mor1kx/verilog/.travis/run-or1k-tests.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+set -x
+
+PATH="$HOME/tools/or1k-elf/bin:${PATH}"
+PATH="$HOME/tools/bin:${PATH}"
+export PATH
+
+# allow overriding root dir if we aren't running in travis
+if [ -z $OR1K_TESTS_ROOT ] ; then
+  OR1K_TESTS_ROOT=$HOME/src/tools/or1k-tests
+fi
+
+cd $OR1K_TESTS_ROOT/native
+export CORE_ARGS="--pipeline=$PIPELINE $EXTRA_CORE_ARGS"
+export TARGET=mor1kx_tb
+export TARGET_ARGS="--tool=$SIM"
+./runtests.sh $@
+result=$?
+
+if [ $result != 0 ] ; then
+  cat runtests.log
+fi
+exit $result
diff --git a/pythondata_cpu_mor1kx/verilog/.travis/run-verilator.sh b/pythondata_cpu_mor1kx/verilog/.travis/run-verilator.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+export PATH=$HOME/tools/bin:$PATH
+
+verilator --lint-only rtl/verilog/*.v +incdir+rtl/verilog
diff --git a/pythondata_cpu_mor1kx/verilog/.travis/test.sh b/pythondata_cpu_mor1kx/verilog/.travis/test.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+export HOME=/tmp
+
+# Setup fusesoc and add the cores required by or1k-tests
+fusesoc init -y
+fusesoc library add mor1kx-generic https://github.com/stffrdhrn/mor1kx-generic.git
+fusesoc library add intgen https://github.com/stffrdhrn/intgen.git
+fusesoc library add mor1kx /src
+
+cd $HOME/src/tools
+
+cd /src
+
+echo "Running Job $JOB $SIM $PIPELINE"
+echo "Expected failures: $EXPECTED_FAILURES"
+echo "Extra core args: $EXTRA_CORE_ARGS"
+
+./.travis/run-${JOB}.sh
diff --git a/pythondata_cpu_mor1kx/verilog/Jenkinsfile b/pythondata_cpu_mor1kx/verilog/Jenkinsfile
@@ -0,0 +1,83 @@
+openriscPipeline {
+
+    yosysReport {
+		core 'mor1kx'
+		target 'synth'
+		logPath 'build/mor1kx_*/synth-icestorm/yosys.log'
+	}
+
+    job('verilator') {
+        job 'verilator'
+    }
+
+    job('icarus-cappuccino') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy'
+    }
+
+    job('icarus-cappuccino-dmmu-none') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy'
+        extraCoreArgs '--feature_dmmu NONE'
+    }
+
+    job('icarus-cappuccino-immu-none') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy or1k-dsxinsn'
+        extraCoreArgs '--feature_immu NONE'
+    }
+
+    job('icarus-cappuccino-datacache-none') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy'
+        extraCoreArgs '--feature_datacache NONE'
+    }
+
+    job('icarus-cappuccino-instructioncache-none') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy'
+        extraCoreArgs '--feature_instructioncache NONE'
+    }
+
+    job('icarus-cappuccino-debugunit-none') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy'
+        extraCoreArgs '--feature_debugunit NONE'
+    }
+
+    job('icarus-cappuccino-cmov-none') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy or1k-cmov'
+        extraCoreArgs '--feature_cmov NONE'
+    }
+
+    job('icarus-cappuccino-ext-none') {
+        job 'or1k-tests'
+        sim 'icarus'
+        pipeline 'CAPPUCCINO'
+        expectedFailures 'or1k-cy or1k-ext'
+        extraCoreArgs '--feature_ext NONE'
+    }
+
+//    TODO: Fix failing Job
+//
+//    job('icarus-espresso') {
+//        job 'or1k-tests'
+//        sim 'icarus'
+//        pipeline 'ESPRESSO'
+//    }
+}