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This repository has been archived by the owner on Sep 27, 2024. It is now read-only.
Problem: By changing the ADC clock frequency one can be in a condition where the maximum DDR3 memory bandwidth is exceeded. At least a flag indicating this has happened with the current acquisition must be created.
Solution: There is already a flag in the lnls-bpm/bpm-gw gateware and lnls-bpm/halcs software that can be used for this., called FC_FULL status field in the acquisition status register.
lerwys
changed the title
[BPMApp] No checking if acquisition is stalled due to too dast data rates
[BPMApp] Not checking if acquisition is stalled due to too dast data rates
Mar 10, 2018
lerwys
changed the title
[BPMApp] Not checking if acquisition is stalled due to too dast data rates
[BPMApp] Not checking if acquisition is stalled due to too fast data rates
Mar 10, 2018
lerwys
added a commit
to lnls-dig/halcs
that referenced
this issue
Apr 3, 2019
Problem: By changing the ADC clock frequency one can be in a condition where the maximum DDR3 memory bandwidth is exceeded. At least a flag indicating this has happened with the current acquisition must be created.
Solution: There is already a flag in the lnls-bpm/bpm-gw gateware and lnls-bpm/halcs software that can be used for this., called FC_FULL status field in the acquisition status register.
This is related to issue #28.
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