From 403fbea2d93b5cb62faf4f3d0d97247d7430be41 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 18 Apr 2024 16:38:34 -0300 Subject: [PATCH] fofb_shaper_filt: use number of biquads to define order Instead of defining the maximum order, use a generic to define the number of internal biquads (the order is twice this value). This simplifies things since we can use it directly (i.e. no intermediate computation) for defining internal dimensions, number of iterations etc. NOTE: The ABI was broken. The register 'max_filt_order' was changed to 'num_biquads'. --- hdl/ip_cores/infra-cores | 2 +- hdl/modules/fofb_ctrl_pkg.vhd | 4 +-- .../cheby/doc/wb_fofb_shaper_filt_regs.html | 28 +++++++++---------- .../cheby/wb_fofb_shaper_filt_regs.cheby | 11 ++++---- .../cheby/wb_fofb_shaper_filt_regs.h | 22 +++++++-------- .../cheby/wb_fofb_shaper_filt_regs.vhd | 16 +++++------ .../fofb_shaper_filt/fofb_shaper_filt_pkg.vhd | 4 +-- .../fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 24 ++++++++-------- .../wb_fofb_shaper_filt_regs_consts_pkg.vhd | 4 +-- .../xwb_fofb_shaper_filt_tb.vhd | 21 +++++++------- 10 files changed, 65 insertions(+), 71 deletions(-) diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index a11f5cbb..030fc0fd 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit a11f5cbb7848939f7dd67cbee0601728450cd1d9 +Subproject commit 030fc0fdb7583a47495fcaff47a3853855d41b0a diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index d2c0cf45..cd51b441 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -774,7 +774,7 @@ package fofb_ctrl_pkg is constant c_xwb_fofb_shaper_filter_regs_sdb : t_sdb_device := ( abi_class => x"0000", -- undocumented device abi_ver_major => x"00", - abi_ver_minor => x"03", + abi_ver_minor => x"04", wbd_endian => c_sdb_endian_big, wbd_width => x"4", -- 32-bit port granularity (0100) sdb_component => ( @@ -784,7 +784,7 @@ package fofb_ctrl_pkg is vendor_id => x"1000000000001215", -- LNLS device_id => x"f65559b2", -- Last 8 chars of "FOFB_SHAPER_REGS" md5sum version => x"00000001", - date => x"20240412", + date => x"20240418", name => "FOFB_SHAPER_REGS "))); end fofb_ctrl_pkg; diff --git a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html index f44d4206..939b1fa0 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html +++ b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html @@ -314,9 +314,9 @@

1. Memory map summary

0x2000 REG -max_filt_order -max_filt_order -max_filt_order +num_biquads +num_biquads +num_biquads 0x2004 @@ -1192,16 +1192,16 @@

2.12. ch.11.coeffs.val

representation. It should be aligned to the left. - -

2.13. max_filt_order

+ +

2.13. num_biquads

- + - +
HW prefix:max_filt_order
HW prefix:num_biquads
HW address:0x2000
C prefix:max_filt_order
C prefix:num_biquads
C block offset:0x2000

-Maximum filter order supported by the gateware.
+The number of internal biquads each IIR filter has.

@@ -1215,7 +1215,7 @@

2.13. max_filt_order

- + @@ -1228,7 +1228,7 @@

2.13. max_filt_order

- + @@ -1241,7 +1241,7 @@

2.13. max_filt_order

- + @@ -1254,13 +1254,13 @@

2.13. max_filt_order

- +
24
max_filt_order[31:24]num_biquads[31:24]
23 16
max_filt_order[23:16]num_biquads[23:16]
15 8
max_filt_order[15:8]num_biquads[15:8]
7 0
max_filt_order[7:0]num_biquads[7:0]
diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby index 54502139..00bc7ffc 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby @@ -14,8 +14,7 @@ memory-map: memsize: 320 interface: sram description: | - Coefficients for the ceil('max_filt_order'/2) IIR internal - biquads. + Coefficients for the 'num_biquads' IIR internal biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: @@ -30,8 +29,8 @@ memory-map: coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the - coefficients corresponding to the first 'max_filt_order' filters - are meaningful for the gateware. + coefficients corresponding to the first 'num_biquads' biquads are + meaningful for the gateware. children: - reg: name: val @@ -41,11 +40,11 @@ memory-map: Coefficient value using 'coeffs_fp_repr' fixed-point representation. It should be aligned to the left. - reg: - name: max_filt_order + name: num_biquads width: 32 access: ro description: | - Maximum filter order supported by the gateware. + The number of internal biquads each IIR filter has. - reg: name: coeffs_fp_repr width: 32 diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h index 8ceee227..bf6b664c 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h @@ -6,8 +6,7 @@ #define WB_FOFB_SHAPER_FILT_REGS_CH 0x0UL #define WB_FOFB_SHAPER_FILT_REGS_CH_SIZE 512 /* 0x200 */ -/* Coefficients for the ceil('max_filt_order'/2) IIR internal -biquads. +/* Coefficients for the 'num_biquads' IIR internal biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: @@ -22,8 +21,8 @@ The 'coeffs' array should be populated in the following manner: coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the -coefficients corresponding to the first 'max_filt_order' filters -are meaningful for the gateware. +coefficients corresponding to the first 'num_biquads' biquads are +meaningful for the gateware. */ #define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS 0x0UL #define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS_SIZE 4 /* 0x4 */ @@ -33,9 +32,9 @@ representation. It should be aligned to the left. */ #define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS_VAL 0x0UL -/* Maximum filter order supported by the gateware. +/* The number of internal biquads each IIR filter has. */ -#define WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER 0x2000UL +#define WB_FOFB_SHAPER_FILT_REGS_NUM_BIQUADS 0x2000UL /* Fixed-point signed (2's complement) representation of coefficients. The coefficients should be aligned to the left. The fixed-point @@ -53,8 +52,7 @@ represented decimal number. struct wb_fofb_shaper_filt_regs { /* [0x0]: REPEAT (no description) */ struct ch { - /* [0x0]: MEMORY Coefficients for the ceil('max_filt_order'/2) IIR internal -biquads. + /* [0x0]: MEMORY Coefficients for the 'num_biquads' IIR internal biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: @@ -69,8 +67,8 @@ The 'coeffs' array should be populated in the following manner: coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the -coefficients corresponding to the first 'max_filt_order' filters -are meaningful for the gateware. +coefficients corresponding to the first 'num_biquads' biquads are +meaningful for the gateware. */ struct coeffs { /* [0x0]: REG (rw) Coefficient value using 'coeffs_fp_repr' fixed-point @@ -86,9 +84,9 @@ representation. It should be aligned to the left. /* padding to: 0 words */ uint32_t __padding_0[512]; - /* [0x2000]: REG (ro) Maximum filter order supported by the gateware. + /* [0x2000]: REG (ro) The number of internal biquads each IIR filter has. */ - uint32_t max_filt_order; + uint32_t num_biquads; /* [0x2004]: REG (ro) Fixed-point signed (2's complement) representation of coefficients. The coefficients should be aligned to the left. The fixed-point diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd index 58177e08..2c7b24ca 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd @@ -1,6 +1,6 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Fri Apr 12 13:09:19 2024 by guilherme.ricioli +-- Generated on Thu Apr 18 16:32:06 2024 by guilherme.ricioli library ieee; @@ -87,9 +87,9 @@ entity wb_fofb_shaper_filt_regs is ch_11_coeffs_data_o : out std_logic_vector(31 downto 0); ch_11_coeffs_wr_o : out std_logic; - -- Maximum filter order supported by the gateware. + -- The number of internal biquads each IIR filter has. - max_filt_order_i : in std_logic_vector(31 downto 0); + num_biquads_i : in std_logic_vector(31 downto 0); -- Fixed-point signed (2's complement) representation of coefficients. -- The coefficients should be aligned to the left. The fixed-point @@ -567,7 +567,7 @@ begin end if; end process; - -- Register max_filt_order + -- Register num_biquads -- Register coeffs_fp_repr @@ -640,7 +640,7 @@ begin when "10000" => case wr_adr_d0(8 downto 2) is when "0000000" => - -- Reg max_filt_order + -- Reg num_biquads wr_ack_int <= wr_req_d0; when "0000001" => -- Reg coeffs_fp_repr @@ -662,7 +662,7 @@ begin ch_7_coeffs_data_i, ch_7_coeffs_rack, ch_8_coeffs_data_i, ch_8_coeffs_rack, ch_9_coeffs_data_i, ch_9_coeffs_rack, ch_10_coeffs_data_i, ch_10_coeffs_rack, ch_11_coeffs_data_i, - ch_11_coeffs_rack, max_filt_order_i, coeffs_fp_repr_int_width_i, + ch_11_coeffs_rack, num_biquads_i, coeffs_fp_repr_int_width_i, coeffs_fp_repr_frac_width_i) begin -- By default ack read requests rd_dat_d0 <= (others => 'X'); @@ -742,9 +742,9 @@ begin when "10000" => case adr_int(8 downto 2) is when "0000000" => - -- Reg max_filt_order + -- Reg num_biquads rd_ack_d0 <= rd_req_int; - rd_dat_d0 <= max_filt_order_i; + rd_dat_d0 <= num_biquads_i; when "0000001" => -- Reg coeffs_fp_repr rd_ack_d0 <= rd_req_int; diff --git a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd index 863c38f2..4537a824 100644 --- a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd +++ b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd @@ -26,8 +26,8 @@ LIBRARY work; USE work.wishbone_pkg.ALL; PACKAGE fofb_shaper_filt_pkg IS - -- The maximum filter order supported - CONSTANT c_MAX_FILT_ORDER : NATURAL := 8; + -- The number of internal biquads each IIR filter has + CONSTANT c_NUM_BIQUADS : NATURAL := 4; -- The signed fixed-point representation of filters' coefficients CONSTANT c_COEFF_INT_WIDTH : NATURAL := 2; diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index 0238d610..fd0ca714 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -95,8 +95,6 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS CONSTANT c_MAX_CHANNELS : NATURAL := 12; - CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; - CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_I_IFC_0s : t_wb_fofb_shaper_filt_regs_coeffs_i_ifc := (data => (OTHERS => '0')); CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s : @@ -135,18 +133,18 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS (OTHERS => c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s); SIGNAL coeffs : t_fofb_shaper_filt_coeffs(g_CHANNELS-1 DOWNTO 0)( - c_NUM_OF_BIQUADS_PER_FILT-1 DOWNTO 0)( + c_NUM_BIQUADS-1 DOWNTO 0)( b0(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), b1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), b2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), a1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), a2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH)); - SIGNAL biquad_idx : NATURAL RANGE 0 to c_NUM_OF_BIQUADS_PER_FILT-1 := 0; + SIGNAL biquad_idx : NATURAL RANGE 0 to c_NUM_BIQUADS-1 := 0; SIGNAL coeff_idx : NATURAL RANGE 0 to 4 := 0; BEGIN - ASSERT c_MAX_FILT_ORDER <= 20 - REPORT "ABI supports up to 20th order filters" + ASSERT c_NUM_BIQUADS <= 10 + REPORT "ABI supports up to 20th order filters (i.e. 10 biquads)" SEVERITY ERROR; ASSERT c_COEFF_INT_WIDTH > 1 and c_COEFF_FRAC_WIDTH > 1 and @@ -166,13 +164,13 @@ BEGIN PROCESS(clk_i) IS BEGIN - -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads and each of these - -- has 5 associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). - -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing - -- the 5*c_NUM_OF_BIQUADS_PER_FILT coefficients of each iir_filt. + -- Each iir_filt has c_NUM_BIQUADS biquads and each of these has 5 + -- associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). + -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing the + -- 5*c_NUM_BIQUADS coefficients of each iir_filt. -- -- The address map is: - -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- For biquad_idx in 0 to c_NUM_BIQUADS-1: -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} @@ -234,7 +232,7 @@ BEGIN GENERATE cmp_iir_filt : iir_filt GENERIC MAP ( - g_MAX_FILT_ORDER => c_MAX_FILT_ORDER, + g_NUM_BIQUADS => c_NUM_BIQUADS, g_X_INT_WIDTH => c_SP_WIDTH, g_X_FRAC_WIDTH => 1, -- see note below g_COEFF_INT_WIDTH => c_COEFF_INT_WIDTH, @@ -316,7 +314,7 @@ BEGIN ch_11_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(11).data, ch_11_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).data, ch_11_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).wr, - max_filt_order_i => STD_LOGIC_VECTOR(to_unsigned(c_MAX_FILT_ORDER, 32)), + num_biquads_i => STD_LOGIC_VECTOR(to_unsigned(c_NUM_BIQUADS, 32)), coeffs_fp_repr_int_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_INT_WIDTH, 5)), coeffs_fp_repr_frac_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_FRAC_WIDTH, 5)) ); diff --git a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd index ce1e79ea..723125af 100644 --- a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd +++ b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd @@ -1,6 +1,6 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Fri Apr 12 13:09:19 2024 by guilherme.ricioli +-- Generated on Thu Apr 18 16:32:06 2024 by guilherme.ricioli package wb_fofb_shaper_filt_regs_consts_pkg is constant c_WB_FOFB_SHAPER_FILT_REGS_SIZE : Natural := 8200; @@ -66,7 +66,7 @@ package wb_fofb_shaper_filt_regs_consts_pkg is constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_ADDR : Natural := 16#1600#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR : Natural := 16#2000#; + constant c_WB_FOFB_SHAPER_FILT_REGS_NUM_BIQUADS_ADDR : Natural := 16#2000#; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_ADDR : Natural := 16#2004#; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET : Natural := 0; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET : Natural := 5; diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index a393c6f7..d9f9dcf6 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -51,7 +51,6 @@ ENTITY xwb_fofb_shaper_filt_tb IS END ENTITY xwb_fofb_shaper_filt_tb; ARCHITECTURE test OF xwb_fofb_shaper_filt_tb IS - CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; CONSTANT c_SYS_CLOCK_FREQ : NATURAL := 100_000_000; SIGNAL clk : STD_LOGIC := '0'; @@ -84,14 +83,14 @@ BEGIN -- Reads maximum filter order read32_pl(clk, wb_slave_i, wb_slave_o, - c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR, v_wb_dat); + c_WB_FOFB_SHAPER_FILT_REGS_NUM_BIQUADS_ADDR, v_wb_dat); - ASSERT to_integer(UNSIGNED(v_wb_dat)) = c_MAX_FILT_ORDER + ASSERT to_integer(UNSIGNED(v_wb_dat)) = c_NUM_BIQUADS REPORT - "UNEXPECTED MAXIMUM FILTER ORDER: " + "UNEXPECTED NUMBER OF BIQUADS: " & NATURAL'image(to_integer(UNSIGNED(v_wb_dat))) & " (EXPECTED: " - & NATURAL'image(c_MAX_FILT_ORDER) & ")" + & NATURAL'image(c_NUM_BIQUADS) & ")" SEVERITY ERROR; -- Read coefficients' fixed-point representation @@ -125,13 +124,13 @@ BEGIN & NATURAL'image(c_COEFF_FRAC_WIDTH) & ")" SEVERITY ERROR; - -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads and each of these - -- has 5 associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). - -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing - -- the 5*c_NUM_OF_BIQUADS_PER_FILT coefficients of each iir_filt. + -- Each iir_filt has c_NUM_BIQUADS biquads and each of these has 5 + -- associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). + -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing the + -- 5*c_NUM_BIQUADS coefficients of each iir_filt. -- -- The address map is: - -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- For biquad_idx in 0 to c_NUM_BIQUADS-1: -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} @@ -147,7 +146,7 @@ BEGIN ch_idx*c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE; readline(fin, lin); - FOR biquad_idx IN 0 TO c_NUM_OF_BIQUADS_PER_FILT-1 + FOR biquad_idx IN 0 TO c_NUM_BIQUADS-1 LOOP FOR coeff_idx IN 0 TO 4 LOOP