diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index a1034c04..0ec9f066 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit a1034c04875eb49ac2ab82f4d37a07c72892bcd9 +Subproject commit 0ec9f06630ebbbdd1514a991a26d977f25553781 diff --git a/hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh b/hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh new file mode 100755 index 00000000..4121ce35 --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +mkdir -p doc +cheby -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby new file mode 100644 index 00000000..a6491b71 --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby @@ -0,0 +1,83 @@ +memory-map: + bus: wb-32-be + name: wb_iir_filt_regs + description: Interface to FOFB IIR shaper filters regs + x-hdl: + busgroup: True + iogroup: wb_iir_filt_regs_ifc + children: + - repeat: + name: ch + count: 12 + children: + - memory: + name: coeffs + memsize: 200 + description: | + Coefficients for the ceil('max_filt_order'/2) IIR internal + biquads. + + Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). + The 'coeffs' array should be populated in the following manner: + + coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + + This array acts like a 'shadow' for the real coefficients and is + only effectived when '1' is written to 'eff_coeffs' bit of 'ctl' + register. + + NOTE: This ABI supports up to 20th order filters, but only the + coefficients corresponding to the first 'max_filt_order' filters + are meaningful for the gateware. + children: + - reg: + name: val + width: 32 + access: rw + description: | + Coefficient value using 'coeffs_fp_repr' fixed-point + representation. It should be aligned to the left. + - reg: + name: max_filt_order + width: 32 + access: ro + description: | + Maximum filter order supported by the gateware. + - reg: + name: coeffs_fp_repr + width: 32 + access: ro + description: | + Fixed-point representation of coefficients. + children: + - field: + name: int_width + range: 4-0 + description: | + Integer width. + - field: + name: frac_width + range: 9-5 + description: | + Fractionary width. + - reg: + name: ctl + width: 32 + access: rw + description: | + Control register. + children: + - field: + name: eff_coeffs + x-hdl: + type: autoclear + range: 0 + description: | + Strobe for effectivating (i.e. updating) coefficients. + comment: | + write 0: no effect + write 1: effectivates coefficients (this bit autoclears) diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h new file mode 100644 index 00000000..8eb50a3c --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h @@ -0,0 +1,98 @@ +#ifndef __CHEBY__WB_IIR_FILT_REGS__H__ +#define __CHEBY__WB_IIR_FILT_REGS__H__ +#define WB_IIR_FILT_REGS_SIZE 4108 /* 0x100c */ + +/* None */ +#define WB_IIR_FILT_REGS_CH 0x0UL +#define WB_IIR_FILT_REGS_CH_SIZE 256 /* 0x100 */ + +/* Coefficients for the ceil('max_filt_order'/2) IIR internal +biquads. + +Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). +The 'coeffs' array should be populated in the following manner: + + coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + +This array acts like a 'shadow' for the real coefficients and is +only effectived when '1' is written to 'eff_coeffs' bit of 'ctl' +register. + +NOTE: This ABI supports up to 20th order filters, but only the +coefficients corresponding to the first 'max_filt_order' filters +are meaningful for the gateware. + */ +#define WB_IIR_FILT_REGS_CH_COEFFS 0x0UL +#define WB_IIR_FILT_REGS_CH_COEFFS_SIZE 4 /* 0x4 */ + +/* Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + */ +#define WB_IIR_FILT_REGS_CH_COEFFS_VAL 0x0UL + +/* Maximum filter order supported by the gateware. + */ +#define WB_IIR_FILT_REGS_MAX_FILT_ORDER 0x1000UL + +/* Fixed-point representation of coefficients. + */ +#define WB_IIR_FILT_REGS_COEFFS_FP_REPR 0x1004UL +#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_MASK 0x1fUL +#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_SHIFT 0 +#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_MASK 0x3e0UL +#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_SHIFT 5 + +/* Control register. + */ +#define WB_IIR_FILT_REGS_CTL 0x1008UL +#define WB_IIR_FILT_REGS_CTL_EFF_COEFFS 0x1UL + +struct wb_iir_filt_regs { + /* [0x0]: REPEAT (no description) */ + struct ch { + /* [0x0]: MEMORY Coefficients for the ceil('max_filt_order'/2) IIR internal +biquads. + +Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). +The 'coeffs' array should be populated in the following manner: + + coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + +This array acts like a 'shadow' for the real coefficients and is +only effectived when '1' is written to 'eff_coeffs' bit of 'ctl' +register. + +NOTE: This ABI supports up to 20th order filters, but only the +coefficients corresponding to the first 'max_filt_order' filters +are meaningful for the gateware. + */ + struct coeffs { + /* [0x0]: REG (rw) Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + */ + uint32_t val; + } coeffs[50]; + } ch[12]; + + /* [0x1000]: REG (ro) Maximum filter order supported by the gateware. + */ + uint32_t max_filt_order; + + /* [0x1004]: REG (ro) Fixed-point representation of coefficients. + */ + uint32_t coeffs_fp_repr; + + /* [0x1008]: REG (rw) Control register. + */ + uint32_t ctl; +}; + +#endif /* __CHEBY__WB_IIR_FILT_REGS__H__ */ diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd new file mode 100644 index 00000000..4a365a99 --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd @@ -0,0 +1,1018 @@ +-- Do not edit. Generated on Wed Sep 20 17:50:17 2023 by guilherme.ricioli +-- With Cheby 1.4.0 and these options: +-- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_pkg.all; +use work.cheby_pkg.all; + +package wb_iir_filt_regs_pkg is + type t_wb_iir_filt_regs_ifc_master_out is record + ch_0_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_1_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_2_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_3_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_4_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_5_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_6_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_7_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_8_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_9_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_10_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_11_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ctl_eff_coeffs : std_logic; + end record t_wb_iir_filt_regs_ifc_master_out; + subtype t_wb_iir_filt_regs_ifc_slave_in is t_wb_iir_filt_regs_ifc_master_out; + + type t_wb_iir_filt_regs_ifc_slave_out is record + ch_0_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_0_coeffs_val_rd_i : std_logic; + ch_1_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_1_coeffs_val_rd_i : std_logic; + ch_2_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_2_coeffs_val_rd_i : std_logic; + ch_3_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_3_coeffs_val_rd_i : std_logic; + ch_4_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_4_coeffs_val_rd_i : std_logic; + ch_5_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_5_coeffs_val_rd_i : std_logic; + ch_6_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_6_coeffs_val_rd_i : std_logic; + ch_7_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_7_coeffs_val_rd_i : std_logic; + ch_8_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_8_coeffs_val_rd_i : std_logic; + ch_9_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_9_coeffs_val_rd_i : std_logic; + ch_10_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_10_coeffs_val_rd_i : std_logic; + ch_11_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_11_coeffs_val_rd_i : std_logic; + max_filt_order : std_logic_vector(31 downto 0); + coeffs_fp_repr_int_width : std_logic_vector(4 downto 0); + coeffs_fp_repr_frac_width : std_logic_vector(4 downto 0); + end record t_wb_iir_filt_regs_ifc_slave_out; + subtype t_wb_iir_filt_regs_ifc_master_in is t_wb_iir_filt_regs_ifc_slave_out; +end wb_iir_filt_regs_pkg; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_pkg.all; +use work.cheby_pkg.all; +use work.wb_iir_filt_regs_pkg.all; + +entity wb_iir_filt_regs is + port ( + rst_n_i : in std_logic; + clk_i : in std_logic; + wb_i : in t_wishbone_slave_in; + wb_o : out t_wishbone_slave_out; + -- Wires and registers + wb_iir_filt_regs_ifc_i : in t_wb_iir_filt_regs_ifc_master_in; + wb_iir_filt_regs_ifc_o : out t_wb_iir_filt_regs_ifc_master_out + ); +end wb_iir_filt_regs; + +architecture syn of wb_iir_filt_regs is + signal adr_int : std_logic_vector(12 downto 2); + signal rd_req_int : std_logic; + signal wr_req_int : std_logic; + signal rd_ack_int : std_logic; + signal wr_ack_int : std_logic; + signal wb_en : std_logic; + signal ack_int : std_logic; + signal wb_rip : std_logic; + signal wb_wip : std_logic; + signal ch_0_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_0_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_0_coeffs_val_rreq : std_logic; + signal ch_0_coeffs_val_rack : std_logic; + signal ch_0_coeffs_val_int_wr : std_logic; + signal ch_1_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_1_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_1_coeffs_val_rreq : std_logic; + signal ch_1_coeffs_val_rack : std_logic; + signal ch_1_coeffs_val_int_wr : std_logic; + signal ch_2_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_2_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_2_coeffs_val_rreq : std_logic; + signal ch_2_coeffs_val_rack : std_logic; + signal ch_2_coeffs_val_int_wr : std_logic; + signal ch_3_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_3_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_3_coeffs_val_rreq : std_logic; + signal ch_3_coeffs_val_rack : std_logic; + signal ch_3_coeffs_val_int_wr : std_logic; + signal ch_4_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_4_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_4_coeffs_val_rreq : std_logic; + signal ch_4_coeffs_val_rack : std_logic; + signal ch_4_coeffs_val_int_wr : std_logic; + signal ch_5_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_5_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_5_coeffs_val_rreq : std_logic; + signal ch_5_coeffs_val_rack : std_logic; + signal ch_5_coeffs_val_int_wr : std_logic; + signal ch_6_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_6_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_6_coeffs_val_rreq : std_logic; + signal ch_6_coeffs_val_rack : std_logic; + signal ch_6_coeffs_val_int_wr : std_logic; + signal ch_7_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_7_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_7_coeffs_val_rreq : std_logic; + signal ch_7_coeffs_val_rack : std_logic; + signal ch_7_coeffs_val_int_wr : std_logic; + signal ch_8_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_8_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_8_coeffs_val_rreq : std_logic; + signal ch_8_coeffs_val_rack : std_logic; + signal ch_8_coeffs_val_int_wr : std_logic; + signal ch_9_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_9_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_9_coeffs_val_rreq : std_logic; + signal ch_9_coeffs_val_rack : std_logic; + signal ch_9_coeffs_val_int_wr : std_logic; + signal ch_10_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_10_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_10_coeffs_val_rreq : std_logic; + signal ch_10_coeffs_val_rack : std_logic; + signal ch_10_coeffs_val_int_wr : std_logic; + signal ch_11_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_11_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_11_coeffs_val_rreq : std_logic; + signal ch_11_coeffs_val_rack : std_logic; + signal ch_11_coeffs_val_int_wr : std_logic; + signal ctl_eff_coeffs_reg : std_logic; + signal ctl_wreq : std_logic; + signal ctl_wack : std_logic; + signal rd_ack_d0 : std_logic; + signal rd_dat_d0 : std_logic_vector(31 downto 0); + signal wr_req_d0 : std_logic; + signal wr_adr_d0 : std_logic_vector(12 downto 2); + signal wr_dat_d0 : std_logic_vector(31 downto 0); + signal wr_sel_d0 : std_logic_vector(3 downto 0); + signal ch_0_coeffs_wr : std_logic; + signal ch_0_coeffs_rr : std_logic; + signal ch_0_coeffs_wreq : std_logic; + signal ch_0_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_1_coeffs_wr : std_logic; + signal ch_1_coeffs_rr : std_logic; + signal ch_1_coeffs_wreq : std_logic; + signal ch_1_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_2_coeffs_wr : std_logic; + signal ch_2_coeffs_rr : std_logic; + signal ch_2_coeffs_wreq : std_logic; + signal ch_2_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_3_coeffs_wr : std_logic; + signal ch_3_coeffs_rr : std_logic; + signal ch_3_coeffs_wreq : std_logic; + signal ch_3_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_4_coeffs_wr : std_logic; + signal ch_4_coeffs_rr : std_logic; + signal ch_4_coeffs_wreq : std_logic; + signal ch_4_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_5_coeffs_wr : std_logic; + signal ch_5_coeffs_rr : std_logic; + signal ch_5_coeffs_wreq : std_logic; + signal ch_5_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_6_coeffs_wr : std_logic; + signal ch_6_coeffs_rr : std_logic; + signal ch_6_coeffs_wreq : std_logic; + signal ch_6_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_7_coeffs_wr : std_logic; + signal ch_7_coeffs_rr : std_logic; + signal ch_7_coeffs_wreq : std_logic; + signal ch_7_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_8_coeffs_wr : std_logic; + signal ch_8_coeffs_rr : std_logic; + signal ch_8_coeffs_wreq : std_logic; + signal ch_8_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_9_coeffs_wr : std_logic; + signal ch_9_coeffs_rr : std_logic; + signal ch_9_coeffs_wreq : std_logic; + signal ch_9_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_10_coeffs_wr : std_logic; + signal ch_10_coeffs_rr : std_logic; + signal ch_10_coeffs_wreq : std_logic; + signal ch_10_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_11_coeffs_wr : std_logic; + signal ch_11_coeffs_rr : std_logic; + signal ch_11_coeffs_wreq : std_logic; + signal ch_11_coeffs_adr_int : std_logic_vector(5 downto 0); +begin + + -- WB decode signals + adr_int <= wb_i.adr(12 downto 2); + wb_en <= wb_i.cyc and wb_i.stb; + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_rip <= '0'; + else + wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int; + end if; + end if; + end process; + rd_req_int <= (wb_en and not wb_i.we) and not wb_rip; + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_wip <= '0'; + else + wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int; + end if; + end if; + end process; + wr_req_int <= (wb_en and wb_i.we) and not wb_wip; + + ack_int <= rd_ack_int or wr_ack_int; + wb_o.ack <= ack_int; + wb_o.stall <= not ack_int and wb_en; + wb_o.rty <= '0'; + wb_o.err <= '0'; + + -- pipelining for wr-in+rd-out + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + rd_ack_int <= '0'; + wr_req_d0 <= '0'; + else + rd_ack_int <= rd_ack_d0; + wb_o.dat <= rd_dat_d0; + wr_req_d0 <= wr_req_int; + wr_adr_d0 <= adr_int; + wr_dat_d0 <= wb_i.dat; + wr_sel_d0 <= wb_i.sel; + end if; + end if; + end process; + + -- Memory ch_0_coeffs + process (adr_int, wr_adr_d0, ch_0_coeffs_wr) begin + if ch_0_coeffs_wr = '1' then + ch_0_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_0_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_0_coeffs_wreq <= ch_0_coeffs_val_int_wr; + ch_0_coeffs_rr <= ch_0_coeffs_val_rreq and not ch_0_coeffs_wreq; + ch_0_coeffs_wr <= ch_0_coeffs_wreq; + ch_0_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_0_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_0_coeffs_val_int_dato, + rd_a_i => ch_0_coeffs_val_rreq, + wr_a_i => ch_0_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_0_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_0_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_0_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_0_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_coeffs_val_rack <= '0'; + else + ch_0_coeffs_val_rack <= ch_0_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_1_coeffs + process (adr_int, wr_adr_d0, ch_1_coeffs_wr) begin + if ch_1_coeffs_wr = '1' then + ch_1_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_1_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_1_coeffs_wreq <= ch_1_coeffs_val_int_wr; + ch_1_coeffs_rr <= ch_1_coeffs_val_rreq and not ch_1_coeffs_wreq; + ch_1_coeffs_wr <= ch_1_coeffs_wreq; + ch_1_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_1_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_1_coeffs_val_int_dato, + rd_a_i => ch_1_coeffs_val_rreq, + wr_a_i => ch_1_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_1_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_1_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_1_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_1_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_coeffs_val_rack <= '0'; + else + ch_1_coeffs_val_rack <= ch_1_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_2_coeffs + process (adr_int, wr_adr_d0, ch_2_coeffs_wr) begin + if ch_2_coeffs_wr = '1' then + ch_2_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_2_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_2_coeffs_wreq <= ch_2_coeffs_val_int_wr; + ch_2_coeffs_rr <= ch_2_coeffs_val_rreq and not ch_2_coeffs_wreq; + ch_2_coeffs_wr <= ch_2_coeffs_wreq; + ch_2_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_2_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_2_coeffs_val_int_dato, + rd_a_i => ch_2_coeffs_val_rreq, + wr_a_i => ch_2_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_2_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_2_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_2_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_2_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_coeffs_val_rack <= '0'; + else + ch_2_coeffs_val_rack <= ch_2_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_3_coeffs + process (adr_int, wr_adr_d0, ch_3_coeffs_wr) begin + if ch_3_coeffs_wr = '1' then + ch_3_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_3_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_3_coeffs_wreq <= ch_3_coeffs_val_int_wr; + ch_3_coeffs_rr <= ch_3_coeffs_val_rreq and not ch_3_coeffs_wreq; + ch_3_coeffs_wr <= ch_3_coeffs_wreq; + ch_3_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_3_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_3_coeffs_val_int_dato, + rd_a_i => ch_3_coeffs_val_rreq, + wr_a_i => ch_3_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_3_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_3_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_3_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_3_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_coeffs_val_rack <= '0'; + else + ch_3_coeffs_val_rack <= ch_3_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_4_coeffs + process (adr_int, wr_adr_d0, ch_4_coeffs_wr) begin + if ch_4_coeffs_wr = '1' then + ch_4_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_4_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_4_coeffs_wreq <= ch_4_coeffs_val_int_wr; + ch_4_coeffs_rr <= ch_4_coeffs_val_rreq and not ch_4_coeffs_wreq; + ch_4_coeffs_wr <= ch_4_coeffs_wreq; + ch_4_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_4_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_4_coeffs_val_int_dato, + rd_a_i => ch_4_coeffs_val_rreq, + wr_a_i => ch_4_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_4_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_4_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_4_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_4_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_coeffs_val_rack <= '0'; + else + ch_4_coeffs_val_rack <= ch_4_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_5_coeffs + process (adr_int, wr_adr_d0, ch_5_coeffs_wr) begin + if ch_5_coeffs_wr = '1' then + ch_5_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_5_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_5_coeffs_wreq <= ch_5_coeffs_val_int_wr; + ch_5_coeffs_rr <= ch_5_coeffs_val_rreq and not ch_5_coeffs_wreq; + ch_5_coeffs_wr <= ch_5_coeffs_wreq; + ch_5_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_5_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_5_coeffs_val_int_dato, + rd_a_i => ch_5_coeffs_val_rreq, + wr_a_i => ch_5_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_5_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_5_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_5_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_5_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_coeffs_val_rack <= '0'; + else + ch_5_coeffs_val_rack <= ch_5_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_6_coeffs + process (adr_int, wr_adr_d0, ch_6_coeffs_wr) begin + if ch_6_coeffs_wr = '1' then + ch_6_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_6_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_6_coeffs_wreq <= ch_6_coeffs_val_int_wr; + ch_6_coeffs_rr <= ch_6_coeffs_val_rreq and not ch_6_coeffs_wreq; + ch_6_coeffs_wr <= ch_6_coeffs_wreq; + ch_6_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_6_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_6_coeffs_val_int_dato, + rd_a_i => ch_6_coeffs_val_rreq, + wr_a_i => ch_6_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_6_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_6_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_6_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_6_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_coeffs_val_rack <= '0'; + else + ch_6_coeffs_val_rack <= ch_6_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_7_coeffs + process (adr_int, wr_adr_d0, ch_7_coeffs_wr) begin + if ch_7_coeffs_wr = '1' then + ch_7_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_7_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_7_coeffs_wreq <= ch_7_coeffs_val_int_wr; + ch_7_coeffs_rr <= ch_7_coeffs_val_rreq and not ch_7_coeffs_wreq; + ch_7_coeffs_wr <= ch_7_coeffs_wreq; + ch_7_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_7_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_7_coeffs_val_int_dato, + rd_a_i => ch_7_coeffs_val_rreq, + wr_a_i => ch_7_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_7_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_7_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_7_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_7_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_coeffs_val_rack <= '0'; + else + ch_7_coeffs_val_rack <= ch_7_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_8_coeffs + process (adr_int, wr_adr_d0, ch_8_coeffs_wr) begin + if ch_8_coeffs_wr = '1' then + ch_8_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_8_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_8_coeffs_wreq <= ch_8_coeffs_val_int_wr; + ch_8_coeffs_rr <= ch_8_coeffs_val_rreq and not ch_8_coeffs_wreq; + ch_8_coeffs_wr <= ch_8_coeffs_wreq; + ch_8_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_8_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_8_coeffs_val_int_dato, + rd_a_i => ch_8_coeffs_val_rreq, + wr_a_i => ch_8_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_8_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_8_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_8_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_8_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_coeffs_val_rack <= '0'; + else + ch_8_coeffs_val_rack <= ch_8_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_9_coeffs + process (adr_int, wr_adr_d0, ch_9_coeffs_wr) begin + if ch_9_coeffs_wr = '1' then + ch_9_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_9_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_9_coeffs_wreq <= ch_9_coeffs_val_int_wr; + ch_9_coeffs_rr <= ch_9_coeffs_val_rreq and not ch_9_coeffs_wreq; + ch_9_coeffs_wr <= ch_9_coeffs_wreq; + ch_9_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_9_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_9_coeffs_val_int_dato, + rd_a_i => ch_9_coeffs_val_rreq, + wr_a_i => ch_9_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_9_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_9_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_9_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_9_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_coeffs_val_rack <= '0'; + else + ch_9_coeffs_val_rack <= ch_9_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_10_coeffs + process (adr_int, wr_adr_d0, ch_10_coeffs_wr) begin + if ch_10_coeffs_wr = '1' then + ch_10_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_10_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_10_coeffs_wreq <= ch_10_coeffs_val_int_wr; + ch_10_coeffs_rr <= ch_10_coeffs_val_rreq and not ch_10_coeffs_wreq; + ch_10_coeffs_wr <= ch_10_coeffs_wreq; + ch_10_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_10_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_10_coeffs_val_int_dato, + rd_a_i => ch_10_coeffs_val_rreq, + wr_a_i => ch_10_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_10_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_10_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_10_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_10_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_coeffs_val_rack <= '0'; + else + ch_10_coeffs_val_rack <= ch_10_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_11_coeffs + process (adr_int, wr_adr_d0, ch_11_coeffs_wr) begin + if ch_11_coeffs_wr = '1' then + ch_11_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_11_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_11_coeffs_wreq <= ch_11_coeffs_val_int_wr; + ch_11_coeffs_rr <= ch_11_coeffs_val_rreq and not ch_11_coeffs_wreq; + ch_11_coeffs_wr <= ch_11_coeffs_wreq; + ch_11_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_11_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_11_coeffs_val_int_dato, + rd_a_i => ch_11_coeffs_val_rreq, + wr_a_i => ch_11_coeffs_val_int_wr, + addr_b_i => wb_iir_filt_regs_ifc_i.ch_11_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_11_coeffs_val_ext_dat, + data_b_o => wb_iir_filt_regs_ifc_o.ch_11_coeffs_val_dat_o, + rd_b_i => wb_iir_filt_regs_ifc_i.ch_11_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_coeffs_val_rack <= '0'; + else + ch_11_coeffs_val_rack <= ch_11_coeffs_val_rreq; + end if; + end if; + end process; + + -- Register max_filt_order + + -- Register coeffs_fp_repr + + -- Register ctl + wb_iir_filt_regs_ifc_o.ctl_eff_coeffs <= ctl_eff_coeffs_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ctl_eff_coeffs_reg <= '0'; + ctl_wack <= '0'; + else + if ctl_wreq = '1' then + ctl_eff_coeffs_reg <= wr_dat_d0(0); + else + ctl_eff_coeffs_reg <= '0'; + end if; + ctl_wack <= ctl_wreq; + end if; + end if; + end process; + + -- Process for write requests. + process (wr_adr_d0, wr_req_d0, ctl_wack) begin + ch_0_coeffs_val_int_wr <= '0'; + ch_1_coeffs_val_int_wr <= '0'; + ch_2_coeffs_val_int_wr <= '0'; + ch_3_coeffs_val_int_wr <= '0'; + ch_4_coeffs_val_int_wr <= '0'; + ch_5_coeffs_val_int_wr <= '0'; + ch_6_coeffs_val_int_wr <= '0'; + ch_7_coeffs_val_int_wr <= '0'; + ch_8_coeffs_val_int_wr <= '0'; + ch_9_coeffs_val_int_wr <= '0'; + ch_10_coeffs_val_int_wr <= '0'; + ch_11_coeffs_val_int_wr <= '0'; + ctl_wreq <= '0'; + case wr_adr_d0(12 downto 8) is + when "00000" => + -- Memory ch_0_coeffs + ch_0_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00001" => + -- Memory ch_1_coeffs + ch_1_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00010" => + -- Memory ch_2_coeffs + ch_2_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00011" => + -- Memory ch_3_coeffs + ch_3_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00100" => + -- Memory ch_4_coeffs + ch_4_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00101" => + -- Memory ch_5_coeffs + ch_5_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00110" => + -- Memory ch_6_coeffs + ch_6_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00111" => + -- Memory ch_7_coeffs + ch_7_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01000" => + -- Memory ch_8_coeffs + ch_8_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01001" => + -- Memory ch_9_coeffs + ch_9_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01010" => + -- Memory ch_10_coeffs + ch_10_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01011" => + -- Memory ch_11_coeffs + ch_11_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "10000" => + case wr_adr_d0(7 downto 2) is + when "000000" => + -- Reg max_filt_order + wr_ack_int <= wr_req_d0; + when "000001" => + -- Reg coeffs_fp_repr + wr_ack_int <= wr_req_d0; + when "000010" => + -- Reg ctl + ctl_wreq <= wr_req_d0; + wr_ack_int <= ctl_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when others => + wr_ack_int <= wr_req_d0; + end case; + end process; + + -- Process for read requests. + process (adr_int, ch_0_coeffs_val_int_dato, rd_req_int, ch_0_coeffs_val_rack, ch_1_coeffs_val_int_dato, ch_1_coeffs_val_rack, ch_2_coeffs_val_int_dato, ch_2_coeffs_val_rack, ch_3_coeffs_val_int_dato, ch_3_coeffs_val_rack, ch_4_coeffs_val_int_dato, ch_4_coeffs_val_rack, ch_5_coeffs_val_int_dato, ch_5_coeffs_val_rack, ch_6_coeffs_val_int_dato, ch_6_coeffs_val_rack, ch_7_coeffs_val_int_dato, ch_7_coeffs_val_rack, ch_8_coeffs_val_int_dato, ch_8_coeffs_val_rack, ch_9_coeffs_val_int_dato, ch_9_coeffs_val_rack, ch_10_coeffs_val_int_dato, ch_10_coeffs_val_rack, ch_11_coeffs_val_int_dato, ch_11_coeffs_val_rack, wb_iir_filt_regs_ifc_i.max_filt_order, wb_iir_filt_regs_ifc_i.coeffs_fp_repr_int_width, wb_iir_filt_regs_ifc_i.coeffs_fp_repr_frac_width) begin + -- By default ack read requests + rd_dat_d0 <= (others => 'X'); + ch_0_coeffs_val_rreq <= '0'; + ch_1_coeffs_val_rreq <= '0'; + ch_2_coeffs_val_rreq <= '0'; + ch_3_coeffs_val_rreq <= '0'; + ch_4_coeffs_val_rreq <= '0'; + ch_5_coeffs_val_rreq <= '0'; + ch_6_coeffs_val_rreq <= '0'; + ch_7_coeffs_val_rreq <= '0'; + ch_8_coeffs_val_rreq <= '0'; + ch_9_coeffs_val_rreq <= '0'; + ch_10_coeffs_val_rreq <= '0'; + ch_11_coeffs_val_rreq <= '0'; + case adr_int(12 downto 8) is + when "00000" => + -- Memory ch_0_coeffs + rd_dat_d0 <= ch_0_coeffs_val_int_dato; + ch_0_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_0_coeffs_val_rack; + when "00001" => + -- Memory ch_1_coeffs + rd_dat_d0 <= ch_1_coeffs_val_int_dato; + ch_1_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_1_coeffs_val_rack; + when "00010" => + -- Memory ch_2_coeffs + rd_dat_d0 <= ch_2_coeffs_val_int_dato; + ch_2_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_2_coeffs_val_rack; + when "00011" => + -- Memory ch_3_coeffs + rd_dat_d0 <= ch_3_coeffs_val_int_dato; + ch_3_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_3_coeffs_val_rack; + when "00100" => + -- Memory ch_4_coeffs + rd_dat_d0 <= ch_4_coeffs_val_int_dato; + ch_4_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_4_coeffs_val_rack; + when "00101" => + -- Memory ch_5_coeffs + rd_dat_d0 <= ch_5_coeffs_val_int_dato; + ch_5_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_5_coeffs_val_rack; + when "00110" => + -- Memory ch_6_coeffs + rd_dat_d0 <= ch_6_coeffs_val_int_dato; + ch_6_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_6_coeffs_val_rack; + when "00111" => + -- Memory ch_7_coeffs + rd_dat_d0 <= ch_7_coeffs_val_int_dato; + ch_7_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_7_coeffs_val_rack; + when "01000" => + -- Memory ch_8_coeffs + rd_dat_d0 <= ch_8_coeffs_val_int_dato; + ch_8_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_8_coeffs_val_rack; + when "01001" => + -- Memory ch_9_coeffs + rd_dat_d0 <= ch_9_coeffs_val_int_dato; + ch_9_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_9_coeffs_val_rack; + when "01010" => + -- Memory ch_10_coeffs + rd_dat_d0 <= ch_10_coeffs_val_int_dato; + ch_10_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_10_coeffs_val_rack; + when "01011" => + -- Memory ch_11_coeffs + rd_dat_d0 <= ch_11_coeffs_val_int_dato; + ch_11_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_11_coeffs_val_rack; + when "10000" => + case adr_int(7 downto 2) is + when "000000" => + -- Reg max_filt_order + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= wb_iir_filt_regs_ifc_i.max_filt_order; + when "000001" => + -- Reg coeffs_fp_repr + rd_ack_d0 <= rd_req_int; + rd_dat_d0(4 downto 0) <= wb_iir_filt_regs_ifc_i.coeffs_fp_repr_int_width; + rd_dat_d0(9 downto 5) <= wb_iir_filt_regs_ifc_i.coeffs_fp_repr_frac_width; + rd_dat_d0(31 downto 10) <= (others => '0'); + when "000010" => + -- Reg ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(31 downto 1) <= (others => '0'); + when others => + rd_ack_d0 <= rd_req_int; + end case; + when others => + rd_ack_d0 <= rd_req_int; + end case; + end process; +end syn;