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Issues list

Support for riscv-formal Component:DV Design verification (DV) or testing issue Type:Enhancement Feature requests, enhancements
#2 opened Jan 2, 2018 by chaosbastler
22
Running ibex-core dv env in questa Type:Question Questions
#2108 opened Nov 29, 2023 by imranjithkumar
@hcallahan-lowrisc
16
Introduce PMA handling to Ibex Component:RTL RTL issue Type:Task Tasks, to-do list.
#764 opened Apr 6, 2020 by GregAC
16
python flow error: dv/uvm/core_ibex/scripts/riscvdv_interface.py", line 165, in get_tool_cmds raise RuntimeError Type:Question Questions
#2095 opened Oct 18, 2023 by A-B-S-Anik
11
Error while installing spike simulator Type:Question Questions
#2011 opened Apr 6, 2023 by raiyyanfaisal09
10
Ease of adapting Ibex memory protocol to tilelink for non 32-bit access Component:RTL RTL issue Type:Task Tasks, to-do list.
#757 opened Apr 1, 2020 by GregAC
10
simulator report error Type:Bug Bugs
#2236 opened Dec 24, 2024 by ha0lyu
9
Is it possible to use newer versions of Verilator and FuseSOC Type:Question Questions
#2116 opened Dec 19, 2023 by Aaronyap2002
9
How do I disable I$ parallel memory request whenever there is a branch and it's a tag hit? Status:FlagToClose No updates received from user after feedback provided. Last chance to raise queries before closure. Type:Question Questions
#1528 opened Feb 11, 2022 by iksw
8
riscv_mmu_stress_test test fail Component:DV Design verification (DV) or testing issue Type:Bug Bugs
#1165 opened Nov 2, 2020 by zjuwlh
@GregAC
8
make[1]: *** [out/metadata/tb.compile.stamp] Error 2 Type:Question Questions
#2071 opened Aug 12, 2023 by cllll402
7
Problem on Building Simulation with RV32E Type:Question Questions
#1860 opened Oct 18, 2022 by sadjadtu
7
Spike log issue Type:Question Questions
#1669 opened May 28, 2022 by shahbazahmad-96
@hcallahan-lowrisc
7
Try out svlint Component:Tool-and-Build Tool and build system related issues Good First Issue Good issue to work on for newcomers Type:Enhancement Feature requests, enhancements
#644 opened Mar 2, 2020 by imphil
7
[tracking] Synthesize Ibex with Yosys Component:DV Design verification (DV) or testing issue Component:RTL RTL issue Type:Task Tasks, to-do list.
#60 opened Jun 5, 2019 by imphil
3 of 5 tasks
7
Writing mseccfg=0x1 will jump to _vectors_start Type:Bug Bugs
#2237 opened Jan 2, 2025 by ha0lyu
6
Missing `ifdef guard from assertion in ibex_core.sv Type:Bug Bugs
#2213 opened Sep 5, 2024 by Kyrhe
@GregAC
6
Spike timeouts in riscv_pmp_full_random_test with experimental-maxperf-pmp-bmfull-icache config Component:DV Design verification (DV) or testing issue Type:Bug Bugs
#1223 opened Jan 7, 2021 by imphil
6
[docs] Clean up line breaks Component:Doc Documentation issue Good First Issue Good issue to work on for newcomers Type:Cleanup Cleanup tasks
#1191 opened Nov 13, 2020 by GregAC
6
Illegal Instruction Retires Type:Bug Bugs
#1132 opened Oct 14, 2020 by shetalani
@tomeroberts
6
How to connect the SRAM generated by the memory compiler to the Ibex core and verify its functionality? Type:Question Questions
#2197 opened Jul 26, 2024 by tju-sun-lab
@GregAC
5
Integration of 6T SRAM with the Ibex core Type:Question Questions
#2194 opened Jul 19, 2024 by kolappanc
5
Cosim mismatch in some tests with PMP enabled using QuestaSim Type:Bug Bugs
#2124 opened Jan 10, 2024 by omarbesta
@GregAC
5
[dv] PMP Coverage Holes Component:DV Design verification (DV) or testing issue Priority:P2
#1944 opened Nov 16, 2022 by GregAC V3
5
Migrate all remaining test sequences to use cosim Component:Test A test or set of tests Component:TestFW Test framework modifications Priority:P2
#1567 opened Mar 16, 2022 by rswarbrick
@hcallahan-lowrisc
5
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