[ci] Reprogram FPGA for each test

As we use different FPGA bitstreams for different analysis targets, make sure to reprogram the FPGA for each test. Signed-off-by: Pascal Nasahl <[email protected]>
lowRISC · Mar 10, 2025 · cd7275e · cd7275e
1 parent 707461a
commit cd7275e
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Showing 8 changed files with 8 additions and 8 deletions.
diff --git a/ci/cfg/ci_capture_ecdsa384_cw310.yaml b/ci/cfg/ci_capture_ecdsa384_cw310.yaml
@@ -1,6 +1,6 @@
 device:
   fpga_bitstream: ../cw/objs/lowrisc_systems_chip_earlgrey_cw310_0.1_ecdsa.bit
-  force_program_bitstream: False
+  force_program_bitstream: True
   fw_bin: ../cw/objs/ecc384_serial_fpga_cw310.bin
   # The clock frequency of the target block is equal to
   # pll_frequency * target_clk_mult. pll_frequency is controllable via

diff --git a/ci/cfg/ci_capture_otbn_vertical_keygen.yaml b/ci/cfg/ci_capture_otbn_vertical_keygen.yaml
@@ -1,6 +1,6 @@
 device:
   fpga_bitstream: ../cw/objs/lowrisc_systems_chip_earlgrey_cw310_0.1_ecdsa.bit
-  force_program_bitstream: False
+  force_program_bitstream: True
   fw_bin: ../cw/objs/otbn_vertical_serial_fpga_cw310.bin
   # The clock frequency of the target block is equal to
   # pll_frequency * target_clk_mult. pll_frequency is controllable via

diff --git a/ci/cfg/ci_capture_otbn_vertical_modinv.yaml b/ci/cfg/ci_capture_otbn_vertical_modinv.yaml
@@ -1,6 +1,6 @@
 device:
   fpga_bitstream: ../cw/objs/lowrisc_systems_chip_earlgrey_cw310_0.1_ecdsa.bit
-  force_program_bitstream: False
+  force_program_bitstream: True
   fw_bin: ../cw/objs/otbn_vertical_serial_fpga_cw310.bin
   # The clock frequency of the target block is equal to
   # pll_frequency * target_clk_mult. pll_frequency is controllable via

diff --git a/ci/cfg/ci_ibex_sca_cw310_ujson.yaml b/ci/cfg/ci_ibex_sca_cw310_ujson.yaml
@@ -1,7 +1,7 @@
 target:
   target_type: cw310
   fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
-  force_program_bitstream: False
+  force_program_bitstream: True
   fw_bin: ../objs/sca_ujson_fpga_cw310.bin
   target_clk_mult: 0.24
   target_freq: 24000000

diff --git a/ci/cfg/ci_kmac_sca_fvsr_cw310_ujson.yaml b/ci/cfg/ci_kmac_sca_fvsr_cw310_ujson.yaml
@@ -1,7 +1,7 @@
 target:
   target_type: cw310
   fpga_bitstream: ../objs/lowrisc_systems_chip_earlgrey_cw310_0.1_kmac.bit
-  force_program_bitstream: False
+  force_program_bitstream: True
   # fw_bin: ../objs/kmac_serial_fpga_cw310.bin
   fw_bin: "../objs/sca_kmac_ujson_fpga_cw310.bin"
   # target_clk_mult is a hardcoded value in the bitstream. Do not change.

diff --git a/ci/cfg/ci_kmac_sca_random_cw310_ujson.yaml b/ci/cfg/ci_kmac_sca_random_cw310_ujson.yaml
@@ -1,7 +1,7 @@
 target:
   target_type: cw310
   fpga_bitstream: ../objs/lowrisc_systems_chip_earlgrey_cw310_0.1_kmac.bit
-  force_program_bitstream: False
+  force_program_bitstream: True
   # fw_bin: ../objs/kmac_serial_fpga_cw310.bin
   fw_bin: "../objs/sca_kmac_ujson_fpga_cw310.bin"
   # target_clk_mult is a hardcoded value in the bitstream. Do not change.

diff --git a/ci/cfg/ci_sha3_sca_fvsr_cw310_ujson.yaml b/ci/cfg/ci_sha3_sca_fvsr_cw310_ujson.yaml
@@ -1,7 +1,7 @@
 target:
   target_type: cw310
   fpga_bitstream: ../objs/lowrisc_systems_chip_earlgrey_cw310_0.1_kmac_dom.bit
-  force_program_bitstream: False
+  force_program_bitstream: True
   # fw_bin: ../objs/sha3_serial_fpga_cw310.bin
   fw_bin: ../objs/sca_ujson_fpga_cw310.bin
   target_clk_mult: 0.24

diff --git a/ci/cfg/ci_sha3_sca_random_cw310_ujson.yaml b/ci/cfg/ci_sha3_sca_random_cw310_ujson.yaml
@@ -1,7 +1,7 @@
 target:
   target_type: cw310
   fpga_bitstream: ../objs/lowrisc_systems_chip_earlgrey_cw310_0.1_kmac_dom.bit
-  force_program_bitstream: False
+  force_program_bitstream: True
   # fw_bin: ../objs/sha3_serial_fpga_cw310.bin
   fw_bin: ../objs/sca_ujson_fpga_cw310.bin
   target_clk_mult: 0.24