-
Notifications
You must be signed in to change notification settings - Fork 54
/
Copy path0033-RISCV-MC-layer-support-for-the-standard-RV32M-instru.patch
163 lines (156 loc) · 6.56 KB
/
0033-RISCV-MC-layer-support-for-the-standard-RV32M-instru.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <[email protected]>
Subject: [RISCV] MC layer support for the standard RV32M instruction set
extension
---
lib/Target/RISCV/RISCV.td | 14 ++++++++++----
lib/Target/RISCV/RISCVInstrInfo.td | 6 ++++++
lib/Target/RISCV/RISCVInstrInfoM.td | 28 ++++++++++++++++++++++++++++
lib/Target/RISCV/RISCVSubtarget.h | 2 ++
test/MC/RISCV/rv32i-invalid.s | 3 +++
test/MC/RISCV/rv32m-valid.s | 33 +++++++++++++++++++++++++++++++++
6 files changed, 82 insertions(+), 4 deletions(-)
create mode 100644 lib/Target/RISCV/RISCVInstrInfoM.td
create mode 100644 test/MC/RISCV/rv32m-valid.s
diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td
index da919acad36..6fc54a517dd 100644
--- a/lib/Target/RISCV/RISCV.td
+++ b/lib/Target/RISCV/RISCV.td
@@ -13,11 +13,17 @@ include "llvm/Target/Target.td"
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
-def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
- "Implements RV64">;
+def FeatureStdExtM
+ : SubtargetFeature<"m", "HasStdExtM", "true",
+ "'M' (Integer Multiplication and Division)">;
+def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
+ AssemblerPredicate<"FeatureStdExtM">;
-def RV64 : HwMode<"+64bit">;
-def RV32 : HwMode<"-64bit">;
+def Feature64Bit
+ : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
+
+def RV64 : HwMode<"+64bit">;
+def RV32 : HwMode<"-64bit">;
//===----------------------------------------------------------------------===//
// Registers, calling conventions, instruction descriptions.
diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td
index 3031a77d0fe..0ea13f7c1d5 100644
--- a/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/lib/Target/RISCV/RISCVInstrInfo.td
@@ -461,3 +461,9 @@ def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(CallSeqEnd timm:$amt1, timm:$amt2)]>;
} // Defs = [X2], Uses = [X2]
+
+//===----------------------------------------------------------------------===//
+// Standard extensions
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrInfoM.td"
diff --git a/lib/Target/RISCV/RISCVInstrInfoM.td b/lib/Target/RISCV/RISCVInstrInfoM.td
new file mode 100644
index 00000000000..a253c1eb811
--- /dev/null
+++ b/lib/Target/RISCV/RISCVInstrInfoM.td
@@ -0,0 +1,28 @@
+//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'M', Integer
+// Multiplication and Division instruction set extension.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtM] in {
+def MUL : ALU_rr<0b0000001, 0b000, "mul">;
+def MULH : ALU_rr<0b0000001, 0b001, "mulh">;
+def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">;
+def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">;
+def DIV : ALU_rr<0b0000001, 0b100, "div">;
+def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
+def REM : ALU_rr<0b0000001, 0b110, "rem">;
+def REMU : ALU_rr<0b0000001, 0b111, "remu">;
+} // Predicates = [HasStdExtM]
diff --git a/lib/Target/RISCV/RISCVSubtarget.h b/lib/Target/RISCV/RISCVSubtarget.h
index cf8956414aa..77510540009 100644
--- a/lib/Target/RISCV/RISCVSubtarget.h
+++ b/lib/Target/RISCV/RISCVSubtarget.h
@@ -30,6 +30,7 @@ class StringRef;
class RISCVSubtarget : public RISCVGenSubtargetInfo {
virtual void anchor();
+ bool HasStdExtM;
bool HasRV64 = false;
unsigned XLen = 32;
MVT XLenVT = MVT::i32;
@@ -66,6 +67,7 @@ public:
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
+ bool hasStdExtM() const { return HasStdExtM; }
bool is64Bit() const { return HasRV64; }
MVT getXLenVT() const { return XLenVT; }
unsigned getXLen() const { return XLen; }
diff --git a/test/MC/RISCV/rv32i-invalid.s b/test/MC/RISCV/rv32i-invalid.s
index 3e4ac85ed60..763d4c547a2 100644
--- a/test/MC/RISCV/rv32i-invalid.s
+++ b/test/MC/RISCV/rv32i-invalid.s
@@ -128,3 +128,6 @@ lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the
# Too few operands
ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+
+# Instruction not in the base ISA
+mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
diff --git a/test/MC/RISCV/rv32m-valid.s b/test/MC/RISCV/rv32m-valid.s
new file mode 100644
index 00000000000..70c1c29d3ad
--- /dev/null
+++ b/test/MC/RISCV/rv32m-valid.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+m -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+m < %s \
+# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+m < %s \
+# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: mul a4, ra, s0
+# CHECK: encoding: [0x33,0x87,0x80,0x02]
+mul a4, ra, s0
+# CHECK-INST: mulh ra, zero, zero
+# CHECK: encoding: [0xb3,0x10,0x00,0x02]
+mulh x1, x0, x0
+# CHECK-INST: mulhsu t0, t2, t1
+# CHECK: encoding: [0xb3,0xa2,0x63,0x02]
+mulhsu t0, t2, t1
+# CHECK-INST: mulhu a5, a4, a3
+# CHECK: encoding: [0xb3,0x37,0xd7,0x02]
+mulhu a5, a4, a3
+# CHECK-INST: div s0, s0, s0
+# CHECK: encoding: [0x33,0x44,0x84,0x02]
+div s0, s0, s0
+# CHECK-INST: divu gp, a0, a1
+# CHECK: encoding: [0xb3,0x51,0xb5,0x02]
+divu gp, a0, a1
+# CHECK-INST: rem s2, s2, s8
+# CHECK: encoding: [0x33,0x69,0x89,0x03]
+rem s2, s2, s8
+# CHECK-INST: remu s2, s2, s8
+# CHECK: encoding: [0x33,0x79,0x89,0x03]
+remu x18, x18, x24
--
2.16.2