lpc1342.mmap

0x40000000 A PERIPHERAL I2C
0x40000000 B  REGISTER CONSET (rw): I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.
0x40000000 C   FIELD 00w02 RESERVED: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40000000 C   FIELD 02w01 AA: Assert acknowledge flag.
0x40000000 C   FIELD 03w01 SI: I2C interrupt flag.
0x40000000 C   FIELD 04w01 STO: STOP flag.
0x40000000 C   FIELD 05w01 STA: START flag.
0x40000000 C   FIELD 06w01 I2EN: I2C interface enable.
0x40000000 C   FIELD 07w25 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000004 B  REGISTER STAT (ro): I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.
0x40000004 C   FIELD 00w03 RESERVED: These bits are unused and are always 0.
0x40000004 C   FIELD 03w05 Status: These bits give the actual status information about the I 2C interface.
0x40000004 C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000008 B  REGISTER DAT (rw): I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
0x40000008 C   FIELD 00w08 Data: This register holds data values that have been received or are to be transmitted.
0x40000008 C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x4000000C B  REGISTER ADR0 (rw): I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
0x4000000C C   FIELD 00w01 GC: General Call enable bit.
0x4000000C C   FIELD 01w07 Address: The I2C device address for slave mode.
0x4000000C C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000010 B  REGISTER SCLH (rw): SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.
0x40000010 C   FIELD 00w16 SCLH: Count for SCL HIGH time period selection.
0x40000010 C   FIELD 16w16 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000014 B  REGISTER SCLL (rw): SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.
0x40000014 C   FIELD 00w16 SCLL: Count for SCL low time period selection.
0x40000014 C   FIELD 16w16 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000018 B  REGISTER CONCLR (wo): I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.
0x40000018 C   FIELD 00w02 RESERVED: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40000018 C   FIELD 02w01 AAC: Assert acknowledge Clear bit.
0x40000018 C   FIELD 03w01 SIC: I2C interrupt Clear bit.
0x40000018 C   FIELD 04w01 RESERVED: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40000018 C   FIELD 05w01 STAC: START flag Clear bit.
0x40000018 C   FIELD 06w01 I2ENC: I2C interface Disable bit.
0x40000018 C   FIELD 07w01 RESERVED: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40000018 C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x4000001C B  REGISTER MMCTRL (rw): Monitor mode control register.
0x4000001C C   FIELD 00w01 MM_ENA: Monitor mode enable.
0x4000001C C   FIELD 01w01 ENA_SCL: SCL output enable.
0x4000001C C   FIELD 02w01 MATCH_ALL: Select interrupt register match.
0x4000001C C   FIELD 03w29 RESERVED: Reserved. The value read from reserved bits is not defined.
0x40000020 B  REGISTER ADR1 (rw): I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
0x40000020 C   FIELD 00w01 GC: General Call enable bit.
0x40000020 C   FIELD 01w07 Address: The I2C device address for slave mode.
0x40000020 C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000024 B  REGISTER ADR2 (rw): I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
0x40000024 C   FIELD 00w01 GC: General Call enable bit.
0x40000024 C   FIELD 01w07 Address: The I2C device address for slave mode.
0x40000024 C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000028 B  REGISTER ADR3 (rw): I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
0x40000028 C   FIELD 00w01 GC: General Call enable bit.
0x40000028 C   FIELD 01w07 Address: The I2C device address for slave mode.
0x40000028 C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x4000002C B  REGISTER DATA_BUFFER (ro): Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.
0x4000002C C   FIELD 00w08 Data: This register holds contents of the 8 MSBs of the I2DAT shift register.
0x4000002C C   FIELD 08w24 RESERVED: Reserved. The value read from a reserved bit is not defined.
0x40000030 B  REGISTER MASK0 (rw): I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
0x40000030 C   FIELD 00w01 RESERVED: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
0x40000030 C   FIELD 01w07 MASK: Mask bits.
0x40000030 C   FIELD 08w24 RESERVED: Reserved. The value read from reserved bits is undefined.
0x40000034 B  REGISTER MASK1 (rw): I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
0x40000034 C   FIELD 00w01 RESERVED: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
0x40000034 C   FIELD 01w07 MASK: Mask bits.
0x40000034 C   FIELD 08w24 RESERVED: Reserved. The value read from reserved bits is undefined.
0x40000038 B  REGISTER MASK2 (rw): I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
0x40000038 C   FIELD 00w01 RESERVED: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
0x40000038 C   FIELD 01w07 MASK: Mask bits.
0x40000038 C   FIELD 08w24 RESERVED: Reserved. The value read from reserved bits is undefined.
0x4000003C B  REGISTER MASK3 (rw): I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
0x4000003C C   FIELD 00w01 RESERVED: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
0x4000003C C   FIELD 01w07 MASK: Mask bits.
0x4000003C C   FIELD 08w24 RESERVED: Reserved. The value read from reserved bits is undefined.
0x40004000 A PERIPHERAL WWDT
0x40004000 B  REGISTER MOD (rw): Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
0x40004000 C   FIELD 00w01 WDEN: Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to watchdog oscillator before setting this bit to one.
0x40004000 C   FIELD 01w01 WDRESET: Watchdog reset enable bit. This bit is Set Only.
0x40004000 C   FIELD 02w01 WDTOF: Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.
0x40004000 C   FIELD 03w01 WDINT: Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
0x40004000 C   FIELD 04w01 WDPROTECT: Watchdog update mode. This bit is Set Only.
0x40004000 C   FIELD 05w27 RESERVED: Reserved. Read value is undefined, only zero should be written.
0x40004004 B  REGISTER TC (rw): Watchdog timer constant register. This register determines the time-out value.
0x40004004 C   FIELD 00w24 Count: Watchdog time-out interval.
0x40004004 C   FIELD 24w08 RESERVED: Reserved. Read value is undefined, only zero should be written.
0x40004008 B  REGISTER FEED (wo): Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
0x40004008 C   FIELD 00w08 Feed: Feed value should be 0xAA followed by 0x55.
0x40004008 C   FIELD 08w24 RESERVED: Reserved
0x4000400C B  REGISTER TV (ro): Watchdog timer value register. This register reads out the current value of the Watchdog timer.
0x4000400C C   FIELD 00w24 Count: Counter timer value.
0x4000400C C   FIELD 24w08 RESERVED: Reserved. Read value is undefined, only zero should be written.
0x40004014 B  REGISTER WARNINT (rw): Watchdog Warning Interrupt compare value.
0x40004014 C   FIELD 00w10 WARNINT: Watchdog warning interrupt compare value.
0x40004014 C   FIELD 10w22 RESERVED: Reserved. Read value is undefined, only zero should be written.
0x40004018 B  REGISTER WINDOW (rw): Watchdog Window compare value.
0x40004018 C   FIELD 00w24 WINDOW: Watchdog window value.
0x40004018 C   FIELD 24w08 RESERVED: Reserved. Read value is undefined, only zero should be written.
0x40008000 A PERIPHERAL UART
0x40008000 B  REGISTER DLL (rw): Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1.
0x40008000 B  REGISTER RBR (ro): Receiver Buffer Register. Contains the next received character to be read. When DLAB=0.
0x40008000 B  REGISTER THR (wo): Transmit Holding Register. The next character to be transmitted is written here. When DLAB=0.
0x40008000 C   FIELD 00w08 DLLSB: The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART.
0x40008000 C   FIELD 00w08 RBR: The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO.
0x40008000 C   FIELD 00w08 THR: Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.
0x40008000 C   FIELD 08w24 RESERVED: Reserved
0x40008000 C   FIELD 08w24 RESERVED: Reserved
0x40008000 C   FIELD 08w24 RESERVED: Reserved
0x40008004 B  REGISTER DLM (rw): Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1.
0x40008004 B  REGISTER IER (rw): Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. When DLAB=0.
0x40008004 C   FIELD 00w01 RBRIE: Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt.
0x40008004 C   FIELD 00w08 DLMSB: The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART.
0x40008004 C   FIELD 01w01 THREIE: Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5].
0x40008004 C   FIELD 02w01 RXLIE: Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].
0x40008004 C   FIELD 03w01 RESERVED: Reserved
0x40008004 C   FIELD 04w03 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008004 C   FIELD 07w01 RESERVED: Reserved
0x40008004 C   FIELD 08w01 ABEOINTEN: Enables the end of auto-baud interrupt.
0x40008004 C   FIELD 08w24 RESERVED: Reserved
0x40008004 C   FIELD 09w01 ABTOINTEN: Enables the auto-baud time-out interrupt.
0x40008004 C   FIELD 10w22 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008008 B  REGISTER FCR (wo): FIFO Control Register. Controls UART FIFO usage and modes.
0x40008008 B  REGISTER IIR (ro): Interrupt ID Register. Identifies which interrupt(s) are pending.
0x40008008 C   FIELD 00w01 FIFOEN: FIFO Enable
0x40008008 C   FIELD 00w01 INTSTATUS: Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].
0x40008008 C   FIELD 01w01 RXFIFOR: RX FIFO Reset
0x40008008 C   FIELD 01w03 INTID: Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).
0x40008008 C   FIELD 02w01 TXFIFOR: TX FIFO Reset
0x40008008 C   FIELD 03w01 RESERVED: Reserved
0x40008008 C   FIELD 04w02 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008008 C   FIELD 04w02 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008008 C   FIELD 06w02 FIFOEN: These bits are equivalent to FCR[0].
0x40008008 C   FIELD 06w02 RXTLVL: RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated.
0x40008008 C   FIELD 08w01 ABEOINT: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
0x40008008 C   FIELD 08w24 RESERVED: Reserved
0x40008008 C   FIELD 09w01 ABTOINT: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
0x40008008 C   FIELD 10w22 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4000800C B  REGISTER LCR (rw): Line Control Register. Contains controls for frame formatting and break generation.
0x4000800C C   FIELD 00w02 WLS: Word Length Select
0x4000800C C   FIELD 02w01 SBS: Stop Bit Select
0x4000800C C   FIELD 03w01 PE: Parity Enable
0x4000800C C   FIELD 04w02 PS: Parity Select
0x4000800C C   FIELD 06w01 BC: Break Control
0x4000800C C   FIELD 07w01 DLAB: Divisor Latch Access Bit (DLAB)
0x4000800C C   FIELD 08w24 RESERVED: Reserved
0x40008010 B  REGISTER MCR (rw): Modem control register
0x40008010 C   FIELD 00w01 DTRCTRL: Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
0x40008010 C   FIELD 01w01 RTSCTRL: Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.
0x40008010 C   FIELD 02w02 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008010 C   FIELD 04w01 LMS: Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.
0x40008010 C   FIELD 05w01 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008010 C   FIELD 06w01 RTSEN: RTS enable
0x40008010 C   FIELD 07w01 CTSEN: CTS enable
0x40008010 C   FIELD 08w24 RESERVED: Reserved
0x40008014 B  REGISTER LSR (ro): Line Status Register. Contains flags for transmit and receive status, including line errors.
0x40008014 C   FIELD 00w01 RDR: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty.
0x40008014 C   FIELD 01w01 OE: Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
0x40008014 C   FIELD 02w01 PE: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
0x40008014 C   FIELD 03w01 FE: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
0x40008014 C   FIELD 04w01 BI: Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
0x40008014 C   FIELD 05w01 THRE: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write.
0x40008014 C   FIELD 06w01 TEMT: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.
0x40008014 C   FIELD 07w01 RXFE: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO.
0x40008014 C   FIELD 08w24 RESERVED: Reserved
0x40008018 B  REGISTER MSR (ro): Modem status register
0x40008018 C   FIELD 00w01 DELTACTS: Set upon state change of input CTS. Cleared on a MSR read.
0x40008018 C   FIELD 01w01 DELTADSR: Set upon state change of input DSR. Cleared on a MSR read.
0x40008018 C   FIELD 02w01 TERI: Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read.
0x40008018 C   FIELD 03w01 DELTADCD: Set upon state change of input DCD. Cleared on a MSR read.
0x40008018 C   FIELD 04w01 CTS: Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.
0x40008018 C   FIELD 05w01 DSR: Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.
0x40008018 C   FIELD 06w01 RI: Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.
0x40008018 C   FIELD 07w01 DCD: Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.
0x40008018 C   FIELD 08w24 RESERVED: Reserved
0x4000801C B  REGISTER SCR (rw): Scratch Pad Register. Eight-bit temporary storage for software.
0x4000801C C   FIELD 00w08 Pad: A readable, writable byte.
0x4000801C C   FIELD 08w24 RESERVED: Reserved
0x40008020 B  REGISTER ACR (rw): Auto-baud Control Register. Contains controls for the auto-baud feature.
0x40008020 C   FIELD 00w01 START: This bit is automatically cleared after auto-baud completion.
0x40008020 C   FIELD 01w01 MODE: Auto-baud mode select bit.
0x40008020 C   FIELD 02w01 AUTORESTART: Auto restart
0x40008020 C   FIELD 03w05 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008020 C   FIELD 08w01 ABEOINTCLR: End of auto-baud interrupt clear bit (write only accessible).
0x40008020 C   FIELD 09w01 ABTOINTCLR: Auto-baud time-out interrupt clear bit (write only accessible).
0x40008020 C   FIELD 10w22 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008028 B  REGISTER FDR (rw): Fractional Divider Register. Generates a clock input for the baud rate divider.
0x40008028 C   FIELD 00w04 DIVADDVAL: Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate.
0x40008028 C   FIELD 04w04 MULVAL: Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not.
0x40008028 C   FIELD 08w24 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008030 B  REGISTER TER (rw): Transmit Enable Register. Turns off UART transmitter for use with software flow control.
0x40008030 C   FIELD 00w07 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008030 C   FIELD 07w01 TXEN: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.
0x40008030 C   FIELD 08w24 RESERVED: Reserved
0x4000804C B  REGISTER RS485CTRL (rw): RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
0x4000804C C   FIELD 00w01 NMMEN: NMM enable
0x4000804C C   FIELD 01w01 RXDIS: Receiver enable
0x4000804C C   FIELD 02w01 AADEN: AAD enable
0x4000804C C   FIELD 03w01 SEL: Direction control pins select
0x4000804C C   FIELD 04w01 DCTRL: Direction control enable
0x4000804C C   FIELD 05w01 OINV: This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
0x4000804C C   FIELD 06w26 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40008050 B  REGISTER RS485ADRMATCH (rw): RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
0x40008050 C   FIELD 00w08 ADRMATCH: Contains the address match value.
0x40008050 C   FIELD 08w24 RESERVED: Reserved
0x40008054 B  REGISTER RS485DLY (rw): RS-485/EIA-485 direction control delay.
0x40008054 C   FIELD 00w08 DLY: Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
0x40008054 C   FIELD 08w24 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4000C000 A PERIPHERAL CT16B0
0x4000C000 B  REGISTER IR (rw): Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
0x4000C000 C   FIELD 00w01 MR0INT: Interrupt flag for match channel 0.
0x4000C000 C   FIELD 01w01 MR1INT: Interrupt flag for match channel 1.
0x4000C000 C   FIELD 02w01 MR2INT: Interrupt flag for match channel 2.
0x4000C000 C   FIELD 03w01 MR3INT: Interrupt flag for match channel 3.
0x4000C000 C   FIELD 04w01 CR0INT: Interrupt flag for capture channel 0 event.
0x4000C000 C   FIELD 05w27 RESERVED: Reserved
0x4000C004 B  REGISTER TCR (rw): Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4000C004 C   FIELD 00w01 CEN: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
0x4000C004 C   FIELD 01w01 CRESET: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
0x4000C004 C   FIELD 02w30 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4000C008 B  REGISTER TC (rw): Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x4000C008 C   FIELD 00w16 TCVAL: Timer counter value.
0x4000C008 C   FIELD 16w16 RESERVED: Reserved.
0x4000C00C B  REGISTER PR (rw): Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
0x4000C00C C   FIELD 00w16 PRVAL: Prescale max value.
0x4000C00C C   FIELD 16w16 RESERVED: Reserved.
0x4000C010 B  REGISTER PC (rw): Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x4000C010 C   FIELD 00w16 PCVAL: Prescale counter value.
0x4000C010 C   FIELD 16w16 RESERVED: Reserved.
0x4000C014 B  REGISTER MCR (rw): Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x4000C014 C   FIELD 00w01 MR0I: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
0x4000C014 C   FIELD 01w01 MR0R: Reset on MR0: the TC will be reset if MR0 matches it.
0x4000C014 C   FIELD 02w01 MR0S: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
0x4000C014 C   FIELD 03w01 MR1I: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
0x4000C014 C   FIELD 04w01 MR1R: Reset on MR1: the TC will be reset if MR1 matches it.
0x4000C014 C   FIELD 05w01 MR1S: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
0x4000C014 C   FIELD 06w01 MR2I: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
0x4000C014 C   FIELD 07w01 MR2R: Reset on MR2: the TC will be reset if MR2 matches it.
0x4000C014 C   FIELD 08w01 MR2S: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
0x4000C014 C   FIELD 09w01 MR3I: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
0x4000C014 C   FIELD 10w01 MR3R: Reset on MR3: the TC will be reset if MR3 matches it.
0x4000C014 C   FIELD 11w01 MR3S: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
0x4000C014 C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4000C018 B  REGISTER MR0 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4000C018 C   FIELD 00w16 MATCH: Timer counter match value.
0x4000C018 C   FIELD 16w16 RESERVED: Reserved.
0x4000C01C B  REGISTER MR1 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4000C01C C   FIELD 00w16 MATCH: Timer counter match value.
0x4000C01C C   FIELD 16w16 RESERVED: Reserved.
0x4000C020 B  REGISTER MR2 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4000C020 C   FIELD 00w16 MATCH: Timer counter match value.
0x4000C020 C   FIELD 16w16 RESERVED: Reserved.
0x4000C024 B  REGISTER MR3 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4000C024 C   FIELD 00w16 MATCH: Timer counter match value.
0x4000C024 C   FIELD 16w16 RESERVED: Reserved.
0x4000C028 B  REGISTER CCR (rw): Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x4000C028 C   FIELD 00w01 CAP0RE: Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x4000C028 C   FIELD 01w01 CAP0FE: Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x4000C028 C   FIELD 02w01 CAP0I: Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
0x4000C028 C   FIELD 03w29 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4000C02C B  REGISTER CR0 (ro): Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.
0x4000C02C C   FIELD 00w16 CAP: Timer counter capture value.
0x4000C02C C   FIELD 16w16 RESERVED: Reserved.
0x4000C03C B  REGISTER EMR (rw): External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].
0x4000C03C C   FIELD 00w01 EM0: External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4000C03C C   FIELD 01w01 EM1: External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4000C03C C   FIELD 02w01 EM2: External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4000C03C C   FIELD 03w01 EM3: External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
0x4000C03C C   FIELD 04w02 EMC0: External Match Control 0. Determines the functionality of External Match 0.
0x4000C03C C   FIELD 06w02 EMC1: External Match Control 1. Determines the functionality of External Match 1.
0x4000C03C C   FIELD 08w02 EMC2: External Match Control 2. Determines the functionality of External Match 2.
0x4000C03C C   FIELD 10w02 EMC3: External Match Control 3. Determines the functionality of External Match 3.
0x4000C03C C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4000C070 B  REGISTER CTCR (rw): Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x4000C070 C   FIELD 00w02 CTM: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
0x4000C070 C   FIELD 02w02 CIS: Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.
0x4000C070 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4000C074 B  REGISTER PWMC (rw): PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].
0x4000C074 C   FIELD 00w01 PWMEN0: PWM channel0 enable
0x4000C074 C   FIELD 01w01 PWMEN1: PWM channel1 enable
0x4000C074 C   FIELD 02w01 PWMEN2: PWM channel2 enable
0x4000C074 C   FIELD 03w01 PWMEN3: PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
0x4000C074 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40010000 A PERIPHERAL CT16B1
0x40010000 B  REGISTER IR (rw): Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
0x40010000 C   FIELD 00w01 MR0INT: Interrupt flag for match channel 0.
0x40010000 C   FIELD 01w01 MR1INT: Interrupt flag for match channel 1.
0x40010000 C   FIELD 02w01 MR2INT: Interrupt flag for match channel 2.
0x40010000 C   FIELD 03w01 MR3INT: Interrupt flag for match channel 3.
0x40010000 C   FIELD 04w01 CR0INT: Interrupt flag for capture channel 0 event.
0x40010000 C   FIELD 05w27 RESERVED: Reserved
0x40010004 B  REGISTER TCR (rw): Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x40010004 C   FIELD 00w01 CEN: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
0x40010004 C   FIELD 01w01 CRESET: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
0x40010004 C   FIELD 02w30 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40010008 B  REGISTER TC (rw): Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x40010008 C   FIELD 00w16 TCVAL: Timer counter value.
0x40010008 C   FIELD 16w16 RESERVED: Reserved.
0x4001000C B  REGISTER PR (rw): Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
0x4001000C C   FIELD 00w16 PRVAL: Prescale max value.
0x4001000C C   FIELD 16w16 RESERVED: Reserved.
0x40010010 B  REGISTER PC (rw): Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x40010010 C   FIELD 00w16 PCVAL: Prescale counter value.
0x40010010 C   FIELD 16w16 RESERVED: Reserved.
0x40010014 B  REGISTER MCR (rw): Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x40010014 C   FIELD 00w01 MR0I: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
0x40010014 C   FIELD 01w01 MR0R: Reset on MR0: the TC will be reset if MR0 matches it.
0x40010014 C   FIELD 02w01 MR0S: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
0x40010014 C   FIELD 03w01 MR1I: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
0x40010014 C   FIELD 04w01 MR1R: Reset on MR1: the TC will be reset if MR1 matches it.
0x40010014 C   FIELD 05w01 MR1S: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
0x40010014 C   FIELD 06w01 MR2I: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
0x40010014 C   FIELD 07w01 MR2R: Reset on MR2: the TC will be reset if MR2 matches it.
0x40010014 C   FIELD 08w01 MR2S: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
0x40010014 C   FIELD 09w01 MR3I: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
0x40010014 C   FIELD 10w01 MR3R: Reset on MR3: the TC will be reset if MR3 matches it.
0x40010014 C   FIELD 11w01 MR3S: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
0x40010014 C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40010018 B  REGISTER MR0 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x40010018 C   FIELD 00w16 MATCH: Timer counter match value.
0x40010018 C   FIELD 16w16 RESERVED: Reserved.
0x4001001C B  REGISTER MR1 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4001001C C   FIELD 00w16 MATCH: Timer counter match value.
0x4001001C C   FIELD 16w16 RESERVED: Reserved.
0x40010020 B  REGISTER MR2 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x40010020 C   FIELD 00w16 MATCH: Timer counter match value.
0x40010020 C   FIELD 16w16 RESERVED: Reserved.
0x40010024 B  REGISTER MR3 (rw): Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x40010024 C   FIELD 00w16 MATCH: Timer counter match value.
0x40010024 C   FIELD 16w16 RESERVED: Reserved.
0x40010028 B  REGISTER CCR (rw): Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x40010028 C   FIELD 00w01 CAP0RE: Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x40010028 C   FIELD 01w01 CAP0FE: Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x40010028 C   FIELD 02w01 CAP0I: Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
0x40010028 C   FIELD 03w29 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4001002C B  REGISTER CR0 (ro): Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.
0x4001002C C   FIELD 00w16 CAP: Timer counter capture value.
0x4001002C C   FIELD 16w16 RESERVED: Reserved.
0x4001003C B  REGISTER EMR (rw): External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].
0x4001003C C   FIELD 00w01 EM0: External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001003C C   FIELD 01w01 EM1: External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001003C C   FIELD 02w01 EM2: External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001003C C   FIELD 03w01 EM3: External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
0x4001003C C   FIELD 04w02 EMC0: External Match Control 0. Determines the functionality of External Match 0.
0x4001003C C   FIELD 06w02 EMC1: External Match Control 1. Determines the functionality of External Match 1.
0x4001003C C   FIELD 08w02 EMC2: External Match Control 2. Determines the functionality of External Match 2.
0x4001003C C   FIELD 10w02 EMC3: External Match Control 3. Determines the functionality of External Match 3.
0x4001003C C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40010070 B  REGISTER CTCR (rw): Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x40010070 C   FIELD 00w02 CTM: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
0x40010070 C   FIELD 02w02 CIS: Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.
0x40010070 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40010074 B  REGISTER PWMC (rw): PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].
0x40010074 C   FIELD 00w01 PWMEN0: PWM channel0 enable
0x40010074 C   FIELD 01w01 PWMEN1: PWM channel1 enable
0x40010074 C   FIELD 02w01 PWMEN2: PWM channel2 enable
0x40010074 C   FIELD 03w01 PWMEN3: PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
0x40010074 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40014000 A PERIPHERAL CT32B0
0x40014000 B  REGISTER IR (rw): Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
0x40014000 C   FIELD 00w01 MR0INT: Interrupt flag for match channel 0.
0x40014000 C   FIELD 01w01 MR1INT: Interrupt flag for match channel 1.
0x40014000 C   FIELD 02w01 MR2INT: Interrupt flag for match channel 2.
0x40014000 C   FIELD 03w01 MR3INT: Interrupt flag for match channel 3.
0x40014000 C   FIELD 04w01 CR0INT: Interrupt flag for capture channel 0 event.
0x40014000 C   FIELD 05w27 RESERVED: Reserved
0x40014004 B  REGISTER TCR (rw): Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x40014004 C   FIELD 00w01 CEN: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
0x40014004 C   FIELD 01w01 CRES: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
0x40014004 C   FIELD 02w30 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40014008 B  REGISTER TC (rw): Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x40014008 C   FIELD 00w32 TCVAL: Timer counter value.
0x4001400C B  REGISTER PR (rw): Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
0x4001400C C   FIELD 00w32 PRVAL: Prescale value.
0x40014010 B  REGISTER PC (rw): Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x40014010 C   FIELD 00w32 PCVAL: Prescale counter value.
0x40014014 B  REGISTER MCR (rw): Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x40014014 C   FIELD 00w01 MR0I: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
0x40014014 C   FIELD 01w01 MR0R: Reset on MR0: the TC will be reset if MR0 matches it.
0x40014014 C   FIELD 02w01 MR0S: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
0x40014014 C   FIELD 03w01 MR1I: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
0x40014014 C   FIELD 04w01 MR1R: Reset on MR1: the TC will be reset if MR1 matches it.
0x40014014 C   FIELD 05w01 MR1S: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
0x40014014 C   FIELD 06w01 MR2I: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
0x40014014 C   FIELD 07w01 MR2R: Reset on MR2: the TC will be reset if MR2 matches it.
0x40014014 C   FIELD 08w01 MR2S: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
0x40014014 C   FIELD 09w01 MR3I: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
0x40014014 C   FIELD 10w01 MR3R: Reset on MR3: the TC will be reset if MR3 matches it.
0x40014014 C   FIELD 11w01 MR3S: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
0x40014014 C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40014018 B  REGISTER MR0 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x40014018 C   FIELD 00w32 MATCH: Timer counter match value.
0x4001401C B  REGISTER MR1 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x4001401C C   FIELD 00w32 MATCH: Timer counter match value.
0x40014020 B  REGISTER MR2 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x40014020 C   FIELD 00w32 MATCH: Timer counter match value.
0x40014024 B  REGISTER MR3 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x40014024 C   FIELD 00w32 MATCH: Timer counter match value.
0x40014028 B  REGISTER CCR (rw): Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x40014028 C   FIELD 00w01 CAP0RE: Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x40014028 C   FIELD 01w01 CAP0FE: Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x40014028 C   FIELD 02w01 CAP0I: Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
0x40014028 C   FIELD 03w29 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4001402C B  REGISTER CR0 (ro): Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input.
0x4001402C C   FIELD 00w32 CAP: Timer counter capture value.
0x4001403C B  REGISTER EMR (rw): External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].
0x4001403C C   FIELD 00w01 EM0: External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001403C C   FIELD 01w01 EM1: External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001403C C   FIELD 02w01 EM2: External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001403C C   FIELD 03w01 EM3: External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001403C C   FIELD 04w02 EMC0: External Match Control 0. Determines the functionality of External Match 0.
0x4001403C C   FIELD 06w02 EMC1: External Match Control 1. Determines the functionality of External Match 1.
0x4001403C C   FIELD 08w02 EMC2: External Match Control 2. Determines the functionality of External Match 2.
0x4001403C C   FIELD 10w02 EMC3: External Match Control 3. Determines the functionality of External Match 3.
0x4001403C C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40014070 B  REGISTER CTCR (rw): Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x40014070 C   FIELD 00w02 CTM: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
0x40014070 C   FIELD 02w02 CIS: Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
0x40014070 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40014074 B  REGISTER PWMC (rw): PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
0x40014074 C   FIELD 00w01 PWMEN0: PWM channel 0 enable
0x40014074 C   FIELD 01w01 PWMEN1: PWM channel 1 enable
0x40014074 C   FIELD 02w01 PWMEN2: PWM channel 2 enable
0x40014074 C   FIELD 03w01 PWMEN3: PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
0x40014074 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40018000 A PERIPHERAL CT32B1
0x40018000 B  REGISTER IR (rw): Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
0x40018000 C   FIELD 00w01 MR0INT: Interrupt flag for match channel 0.
0x40018000 C   FIELD 01w01 MR1INT: Interrupt flag for match channel 1.
0x40018000 C   FIELD 02w01 MR2INT: Interrupt flag for match channel 2.
0x40018000 C   FIELD 03w01 MR3INT: Interrupt flag for match channel 3.
0x40018000 C   FIELD 04w01 CR0INT: Interrupt flag for capture channel 0 event.
0x40018000 C   FIELD 05w27 RESERVED: Reserved
0x40018004 B  REGISTER TCR (rw): Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x40018004 C   FIELD 00w01 CEN: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
0x40018004 C   FIELD 01w01 CRES: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
0x40018004 C   FIELD 02w30 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40018008 B  REGISTER TC (rw): Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x40018008 C   FIELD 00w32 TCVAL: Timer counter value.
0x4001800C B  REGISTER PR (rw): Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
0x4001800C C   FIELD 00w32 PRVAL: Prescale value.
0x40018010 B  REGISTER PC (rw): Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x40018010 C   FIELD 00w32 PCVAL: Prescale counter value.
0x40018014 B  REGISTER MCR (rw): Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x40018014 C   FIELD 00w01 MR0I: Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
0x40018014 C   FIELD 01w01 MR0R: Reset on MR0: the TC will be reset if MR0 matches it.
0x40018014 C   FIELD 02w01 MR0S: Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
0x40018014 C   FIELD 03w01 MR1I: Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
0x40018014 C   FIELD 04w01 MR1R: Reset on MR1: the TC will be reset if MR1 matches it.
0x40018014 C   FIELD 05w01 MR1S: Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
0x40018014 C   FIELD 06w01 MR2I: Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
0x40018014 C   FIELD 07w01 MR2R: Reset on MR2: the TC will be reset if MR2 matches it.
0x40018014 C   FIELD 08w01 MR2S: Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
0x40018014 C   FIELD 09w01 MR3I: Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
0x40018014 C   FIELD 10w01 MR3R: Reset on MR3: the TC will be reset if MR3 matches it.
0x40018014 C   FIELD 11w01 MR3S: Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
0x40018014 C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40018018 B  REGISTER MR0 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x40018018 C   FIELD 00w32 MATCH: Timer counter match value.
0x4001801C B  REGISTER MR1 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x4001801C C   FIELD 00w32 MATCH: Timer counter match value.
0x40018020 B  REGISTER MR2 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x40018020 C   FIELD 00w32 MATCH: Timer counter match value.
0x40018024 B  REGISTER MR3 (rw): Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x40018024 C   FIELD 00w32 MATCH: Timer counter match value.
0x40018028 B  REGISTER CCR (rw): Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x40018028 C   FIELD 00w01 CAP0RE: Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x40018028 C   FIELD 01w01 CAP0FE: Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
0x40018028 C   FIELD 02w01 CAP0I: Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
0x40018028 C   FIELD 03w29 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4001802C B  REGISTER CR0 (ro): Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input.
0x4001802C C   FIELD 00w32 CAP: Timer counter capture value.
0x4001803C B  REGISTER EMR (rw): External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].
0x4001803C C   FIELD 00w01 EM0: External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001803C C   FIELD 01w01 EM1: External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001803C C   FIELD 02w01 EM2: External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001803C C   FIELD 03w01 EM3: External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0x4001803C C   FIELD 04w02 EMC0: External Match Control 0. Determines the functionality of External Match 0.
0x4001803C C   FIELD 06w02 EMC1: External Match Control 1. Determines the functionality of External Match 1.
0x4001803C C   FIELD 08w02 EMC2: External Match Control 2. Determines the functionality of External Match 2.
0x4001803C C   FIELD 10w02 EMC3: External Match Control 3. Determines the functionality of External Match 3.
0x4001803C C   FIELD 12w20 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40018070 B  REGISTER CTCR (rw): Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x40018070 C   FIELD 00w02 CTM: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
0x40018070 C   FIELD 02w02 CIS: Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
0x40018070 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40018074 B  REGISTER PWMC (rw): PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
0x40018074 C   FIELD 00w01 PWMEN0: PWM channel 0 enable
0x40018074 C   FIELD 01w01 PWMEN1: PWM channel 1 enable
0x40018074 C   FIELD 02w01 PWMEN2: PWM channel 2 enable
0x40018074 C   FIELD 03w01 PWMEN3: PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
0x40018074 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4001C000 A PERIPHERAL ADC
0x4001C000 B  REGISTER CR (rw): A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur.
0x4001C000 C   FIELD 00w08 SEL: Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).
0x4001C000 C   FIELD 08w08 CLKDIV: The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
0x4001C000 C   FIELD 16w01 BURST: Burst select
0x4001C000 C   FIELD 17w03 CLKS: This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
0x4001C000 C   FIELD 20w04 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4001C000 C   FIELD 24w03 START: When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
0x4001C000 C   FIELD 27w01 EDGE: This bit is significant only when the START field contains 010-111. In these cases:
0x4001C000 C   FIELD 28w04 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4001C004 B  REGISTER GDR (rw): A/D Global Data Register. Contains the result of the most recent A/D conversion.
0x4001C004 C   FIELD 00w06 RESERVED: Reserved.
0x4001C004 C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
0x4001C004 C   FIELD 16w08 RESERVED: Reserved.
0x4001C004 C   FIELD 24w03 CHN: These bits contain the channel from which the V_VREF bits were converted.
0x4001C004 C   FIELD 27w03 RESERVED: Reserved.
0x4001C004 C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.
0x4001C004 C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
0x4001C00C B  REGISTER INTEN (rw): A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.
0x4001C00C C   FIELD 00w01 ADINTEN0: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 01w01 ADINTEN1: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 02w01 ADINTEN2: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 03w01 ADINTEN3: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 04w01 ADINTEN4: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 05w01 ADINTEN5: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 06w01 ADINTEN6: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 07w01 ADINTEN7: These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
0x4001C00C C   FIELD 08w01 ADGINTEN: When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.
0x4001C00C C   FIELD 09w23 RESERVED: Reserved.
0x4001C010 B  REGISTER DR0 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C010 C   FIELD 00w06 RESERVED: Reserved.
0x4001C010 C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C010 C   FIELD 16w14 RESERVED: Reserved.
0x4001C010 C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C010 C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C014 B  REGISTER DR1 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C014 C   FIELD 00w06 RESERVED: Reserved.
0x4001C014 C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C014 C   FIELD 16w14 RESERVED: Reserved.
0x4001C014 C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C014 C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C018 B  REGISTER DR2 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C018 C   FIELD 00w06 RESERVED: Reserved.
0x4001C018 C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C018 C   FIELD 16w14 RESERVED: Reserved.
0x4001C018 C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C018 C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C01C B  REGISTER DR3 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C01C C   FIELD 00w06 RESERVED: Reserved.
0x4001C01C C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C01C C   FIELD 16w14 RESERVED: Reserved.
0x4001C01C C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C01C C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C020 B  REGISTER DR4 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C020 C   FIELD 00w06 RESERVED: Reserved.
0x4001C020 C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C020 C   FIELD 16w14 RESERVED: Reserved.
0x4001C020 C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C020 C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C024 B  REGISTER DR5 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C024 C   FIELD 00w06 RESERVED: Reserved.
0x4001C024 C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C024 C   FIELD 16w14 RESERVED: Reserved.
0x4001C024 C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C024 C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C028 B  REGISTER DR6 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C028 C   FIELD 00w06 RESERVED: Reserved.
0x4001C028 C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C028 C   FIELD 16w14 RESERVED: Reserved.
0x4001C028 C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C028 C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C02C B  REGISTER DR7 (rw): A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n
0x4001C02C C   FIELD 00w06 RESERVED: Reserved.
0x4001C02C C   FIELD 06w10 V_VREF: When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
0x4001C02C C   FIELD 16w14 RESERVED: Reserved.
0x4001C02C C   FIELD 30w01 OVERRUN: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
0x4001C02C C   FIELD 31w01 DONE: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
0x4001C030 B  REGISTER STAT (ro): A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.
0x4001C030 C   FIELD 00w01 DONE0: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 01w01 DONE1: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 02w01 DONE2: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 03w01 DONE3: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 04w01 DONE4: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 05w01 DONE5: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 06w01 DONE6: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 07w01 DONE7: These bits mirror the DONE status flags that appear in the result register for each A/D channel.
0x4001C030 C   FIELD 08w01 OVERRUN0: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 09w01 OVERRUN1: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 10w01 OVERRUN2: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 11w01 OVERRUN3: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 12w01 OVERRUN4: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 13w01 OVERRUN5: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 14w01 OVERRUN6: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 15w01 OVERRUN7: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
0x4001C030 C   FIELD 16w01 ADINT: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
0x4001C030 C   FIELD 17w15 RESERVED: Reserved.
0x40020000 A PERIPHERAL USB
0x40020000 B  REGISTER DEVINTST (ro): USB Device Interrupt Status
0x40020000 C   FIELD 00w01 FRAME: The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 01w01 EP0: USB core interrupt for physical endpoint 0. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 02w01 EP1: USB core interrupt for physical endpoint 1. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 03w01 EP2: USB core interrupt for physical endpoint 2. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 04w01 EP3: USB core interrupt for physical endpoint 3. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 05w01 EP4: USB core interrupt for physical endpoint 4. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 06w01 EP5: USB core interrupt for physical endpoint 5. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 07w01 EP6: USB core interrupt for physical endpoint 6. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 08w01 EP7: USB core interrupt for physical endpoint 7. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 09w01 DEV_STAT: Set when USB Bus reset, USB suspend change, or Connect change event occurs. Refer to Section 10.11.7. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 10w01 CC_EMPTY: The command code register (USBCmdCode) is empty (New command can be written). 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 11w01 CD_FULL: Command data register (USBCmdData) is full (Data can be read now). 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 12w01 RxENDPKT: The current packet in the endpoint buffer is transferred to the CPU. 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 13w01 TxENDPKT: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no interrupt. 1 = interrupt pending.
0x40020000 C   FIELD 14w18 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020004 B  REGISTER DEVINTEN (rw): USB Device Interrupt Enable
0x40020004 C   FIELD 00w01 FRAME_EN: Frame interrupt . For isochronous packet transfers. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 01w01 EP0_EN: USB core interrupt for physical endpoint 0. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 02w01 EP1_EN: USB core interrupt for physical endpoint 1. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 03w01 EP2_EN: USB core interrupt for physical endpoint 2. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 04w01 EP3_EN: USB core interrupt for physical endpoint 3. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 05w01 EP4_EN: USB core interrupt for physical endpoint 4. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 06w01 EP5_EN: USB core interrupt for physical endpoint 5. 0 = no interrupt. 1 = interrupt pending.
0x40020004 C   FIELD 07w01 EP6_EN: USB core interrupt for physical endpoint 6. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 08w01 EP7_EN: USB core interrupt for physical endpoint 7. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 09w01 DEV_STAT_EN: Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 10w01 CC_EMPTY_EN: The command code register (USBCmdCode) is empty (New command can be written). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 11w01 CD_FULL_EN: Command data register (USBCmdData) is full (Data can be read now). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 12w01 RXENDPKT_EN: The current packet in the endpoint buffer is transferred to the CPU. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 13w01 TXENDPKT_EN: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
0x40020004 C   FIELD 14w18 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020008 B  REGISTER DEVINTCTRL (wo): USB Device Interrupt Clear
0x40020008 C   FIELD 00w01 FRAME_CLR: Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 01w01 EP0_CLR: USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 02w01 EP1_CLR: USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 03w01 EP2_CLR: USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 04w01 EP3_CLR: USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 05w01 EP4_CLR: USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 06w01 EP5_CLR: USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 07w01 EP6_CLR: USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 08w01 EP7_CLR: USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 09w01 DEV_STAT_CLR: Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 10w01 CC_EMPTY_CLR: The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 11w01 CD_FULL_CLR: Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 12w01 RXENDPKT_CLR: The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 13w01 TXENDPKT_CLR: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
0x40020008 C   FIELD 14w18 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4002000C B  REGISTER DEVINTSET (wo): USB Device Interrupt Set
0x4002000C C   FIELD 00w01 FRAME_SET: Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 01w01 EP0_SET: USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 02w01 EP1_SET: USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 03w01 EP2_SET: USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 04w01 EP3_SET: USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 05w01 EP4_SET: USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 06w01 EP5_SET: USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 07w01 EP6_SET: USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 08w01 EP7_SET: USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 09w01 DEV_STAT_SET: Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 10w01 CC_EMPTY_SET: The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 11w01 CD_FULL_SET: Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 12w01 RXENDPKT_SET: The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 13w01 TXENDPKT_SET: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
0x4002000C C   FIELD 14w18 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020010 B  REGISTER CMDCODE (wo): USB Command Code
0x40020010 C   FIELD 00w08 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020010 C   FIELD 08w08 CMD_PHASE: Command phase action
0x40020010 C   FIELD 16w08 CODE_WDATA: This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA).
0x40020010 C   FIELD 24w08 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020014 B  REGISTER CMDDATA (ro): USB Command Data
0x40020014 C   FIELD 00w08 CMD_RDATA: Command Read Data.
0x40020014 C   FIELD 08w24 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020018 B  REGISTER RXDATA (ro): USB Receive Data
0x40020018 C   FIELD 00w32 RX_DATA: Data received.
0x4002001C B  REGISTER TXDATA (wo): USB Transmit Data
0x4002001C C   FIELD 00w32 TX_DATA: Transmit Data.
0x40020020 B  REGISTER RXPLEN (ro): USB Receive Packet Length
0x40020020 C   FIELD 00w10 PKT_LNGTH: The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt.
0x40020020 C   FIELD 10w01 DV: Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.
0x40020020 C   FIELD 11w21 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020024 B  REGISTER TXPLENn (wo): USB Transmit Packet Length
0x40020024 C   FIELD 00w10 PKT_LNGTH: The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.
0x40020024 C   FIELD 10w22 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40020028 B  REGISTER CTRL (rw): USB Control
0x40020028 C   FIELD 00w01 RD_EN: Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.
0x40020028 C   FIELD 01w01 WR_EN: Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.
0x40020028 C   FIELD 02w04 LOG_ENDPOINT: Logical Endpoint number.
0x40020028 C   FIELD 06w26 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4002002C B  REGISTER DEVFIQSEL (wo): USB Device FIQ select
0x4002002C C   FIELD 00w01 FRAME: This interrupt comes from a 1 KHz free running clock resynchronized on the incoming SoF tokens. This is to be used for isochronous packet transfer.
0x4002002C C   FIELD 01w01 BULKOUT: Interrupt routing for bulk out endpoints For logical endpoint 3 (physical endpoints 6 and 7) only.
0x4002002C C   FIELD 02w01 BULKIN: Interrupt routing for bulk in endpoints For logical endpoint 3 (physical endpoints 6 and 7) only.
0x4002002C C   FIELD 03w29 RESERVED: Reserved
0x40038000 A PERIPHERAL PMU
0x40038000 B  REGISTER PCON (rw): Power control register
0x40038000 C   FIELD 00w01 RESERVED: Reserved. Do not write 1 to this bit.
0x40038000 C   FIELD 01w01 DPDEN: Deep power-down mode enable
0x40038000 C   FIELD 02w06 RESERVED: Reserved. Do not write ones to this bit.
0x40038000 C   FIELD 08w01 SLEEPFLAG: Sleep mode flag
0x40038000 C   FIELD 09w02 RESERVED: Reserved. Do not write ones to this bit.
0x40038000 C   FIELD 11w01 DPDFLAG: Deep power-down flag
0x40038000 C   FIELD 12w20 RESERVED: Reserved. Do not write ones to this bit.
0x40038004 B  REGISTER GPREG0 (rw): General purpose register
0x40038004 C   FIELD 00w32 GPDATA: Data retained during Deep power-down mode.
0x40038008 B  REGISTER GPREG1 (rw): General purpose register
0x40038008 C   FIELD 00w32 GPDATA: Data retained during Deep power-down mode.
0x4003800C B  REGISTER GPREG2 (rw): General purpose register
0x4003800C C   FIELD 00w32 GPDATA: Data retained during Deep power-down mode.
0x40038010 B  REGISTER GPREG3 (rw): General purpose register
0x40038010 C   FIELD 00w32 GPDATA: Data retained during Deep power-down mode.
0x40038014 B  REGISTER GPREG4 (rw): General purpose register 4
0x40038014 C   FIELD 00w10 RESERVED: Reserved. Do not write ones to this bit.
0x40038014 C   FIELD 10w01 WAKEUPHYS: WAKEUP pin hysteresis enable
0x40038014 C   FIELD 11w21 GPDATA: Data retained during Deep power-down mode.
0x4003C000 A PERIPHERAL FMC
0x4003C010 B  REGISTER FLASHCFG (rw): Flash configuration register
0x4003C010 C   FIELD 00w02 FLASHTIM: Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
0x4003C010 C   FIELD 02w30 RESERVED: Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read.
0x4003C020 B  REGISTER FMSSTART (rw): Signature start address register
0x4003C020 C   FIELD 00w17 START: Signature generation start address (corresponds to AHB byte address bits[20:4]).
0x4003C020 C   FIELD 17w15 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4003C024 B  REGISTER FMSSTOP (rw): Signature stop-address register
0x4003C024 C   FIELD 00w17 STOP: BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
0x4003C024 C   FIELD 17w01 SIG_START: Start control bit for signature generation.
0x4003C024 C   FIELD 18w14 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4003C02C B  REGISTER FMSW0 (ro): Word 0 [31:0]
0x4003C02C C   FIELD 00w32 SW0_31_0: Word 0 of 128-bit signature (bits 31 to 0).
0x4003C030 B  REGISTER FMSW1 (ro): Word 1 [63:32]
0x4003C030 C   FIELD 00w32 SW1_63_32: Word 1 of 128-bit signature (bits 63 to 32).
0x4003C034 B  REGISTER FMSW2 (ro): Word 2 [95:64]
0x4003C034 C   FIELD 00w32 SW2_95_64: Word 2 of 128-bit signature (bits 95 to 64).
0x4003C038 B  REGISTER FMSW3 (ro): Word 3 [127:96]
0x4003C038 C   FIELD 00w32 SW3_127_96: Word 3 of 128-bit signature (bits 127 to 96).
0x4003CFE0 B  REGISTER FMSTAT (ro): Signature generation status register
0x4003CFE0 C   FIELD 00w02 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4003CFE0 C   FIELD 02w01 SIG_DONE: When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag.
0x4003CFE0 C   FIELD 03w29 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4003CFE8 B  REGISTER FMSTATCLR (wo): Signature generation status clear register
0x4003CFE8 C   FIELD 00w02 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4003CFE8 C   FIELD 02w01 SIG_DONE_CLR: Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
0x4003CFE8 C   FIELD 03w29 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40040000 A PERIPHERAL SSP0
0x40040000 B  REGISTER CR0 (rw): Control Register 0. Selects the serial clock rate, bus type, and data size.
0x40040000 C   FIELD 00w04 DSS: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
0x40040000 C   FIELD 04w02 FRF: Frame Format.
0x40040000 C   FIELD 06w01 CPOL: Clock Out Polarity. This bit is only used in SPI mode.
0x40040000 C   FIELD 07w01 CPHA: Clock Out Phase. This bit is only used in SPI mode.
0x40040000 C   FIELD 08w08 SCR: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR x [SCR+1]).
0x40040000 C   FIELD 16w16 RESERVED: Reserved.
0x40040004 B  REGISTER CR1 (rw): Control Register 1. Selects master/slave and other modes.
0x40040004 C   FIELD 00w01 LBM: Loop Back Mode.
0x40040004 C   FIELD 01w01 SSE: SSP Enable.
0x40040004 C   FIELD 02w01 MS: Master/Slave Mode.This bit can only be written when the SSE bit is 0.
0x40040004 C   FIELD 03w01 SOD: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).
0x40040004 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40040008 B  REGISTER DR (rw): Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
0x40040008 C   FIELD 00w16 DATA: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.
0x40040008 C   FIELD 16w16 RESERVED: Reserved.
0x4004000C B  REGISTER SR (ro): Status Register.
0x4004000C C   FIELD 00w01 TFE: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
0x4004000C C   FIELD 01w01 TNF: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
0x4004000C C   FIELD 02w01 RNE: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
0x4004000C C   FIELD 03w01 RFF: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
0x4004000C C   FIELD 04w01 BSY: Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
0x4004000C C   FIELD 05w27 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40040010 B  REGISTER CPSR (rw): Clock Prescale Register.
0x40040010 C   FIELD 00w08 CPSDVSR: This even value between 2 and 254, by which SSP_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
0x40040010 C   FIELD 08w24 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40040014 B  REGISTER IMSC (rw): Interrupt Mask Set and Clear Register.
0x40040014 C   FIELD 00w01 RORIM: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
0x40040014 C   FIELD 01w01 RTIM: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x40040014 C   FIELD 02w01 RXIM: Software should set this bit to enable interrupt when the Rx FIFO is at least half full.
0x40040014 C   FIELD 03w01 TXIM: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.
0x40040014 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40040018 B  REGISTER RIS (ro): Raw Interrupt Status Register.
0x40040018 C   FIELD 00w01 RORRIS: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
0x40040018 C   FIELD 01w01 RTRIS: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x40040018 C   FIELD 02w01 RXRIS: This bit is 1 if the Rx FIFO is at least half full.
0x40040018 C   FIELD 03w01 TXRIS: This bit is 1 if the Tx FIFO is at least half empty.
0x40040018 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4004001C B  REGISTER MIS (ro): Masked Interrupt Status Register.
0x4004001C C   FIELD 00w01 RORMIS: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
0x4004001C C   FIELD 01w01 RTMIS: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x4004001C C   FIELD 02w01 RXMIS: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
0x4004001C C   FIELD 03w01 TXMIS: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
0x4004001C C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40040020 B  REGISTER ICR (wo): SSPICR Interrupt Clear Register.
0x40040020 C   FIELD 00w01 RORIC: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.
0x40040020 C   FIELD 01w01 RTIC: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read-bit for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x40040020 C   FIELD 02w30 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40044000 A PERIPHERAL IOCON
0x40044000 B  REGISTER PIO2_6 (rw): I/O configuration for pin PIO2_6
0x40044000 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044000 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044000 C   FIELD 05w01 HYS: Hysteresis
0x40044000 C   FIELD 06w04 RESERVED: Reserved
0x40044000 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044000 C   FIELD 11w21 RESERVED: Reserved
0x40044008 B  REGISTER PIO2_0 (rw): I/O configuration for pin PIO2_0/DTR/SSEL1
0x40044008 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044008 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044008 C   FIELD 05w01 HYS: Hysteresis
0x40044008 C   FIELD 06w04 RESERVED: Reserved
0x40044008 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044008 C   FIELD 11w21 RESERVED: Reserved
0x4004400C B  REGISTER RESET_PIO0_0 (rw): I/O configuration for pin RESET/PIO0_0
0x4004400C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004400C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004400C C   FIELD 05w01 HYS: Hysteresis
0x4004400C C   FIELD 06w04 RESERVED: Reserved
0x4004400C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004400C C   FIELD 11w21 RESERVED: Reserved
0x40044010 B  REGISTER PIO0_1 (rw): I/O configuration for pin PIO0_1/CLKOUT/ CT32B0_MAT2/USB_FTOGGLE
0x40044010 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044010 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044010 C   FIELD 05w01 HYS: Hysteresis
0x40044010 C   FIELD 06w04 RESERVED: Reserved
0x40044010 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044010 C   FIELD 11w21 RESERVED: Reserved
0x40044014 B  REGISTER PIO1_8 (rw): I/O configuration for pin PIO1_8/CT16B1_CAP0
0x40044014 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044014 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044014 C   FIELD 05w01 HYS: Hysteresis
0x40044014 C   FIELD 06w04 RESERVED: Reserved
0x40044014 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044014 C   FIELD 11w21 RESERVED: Reserved
0x4004401C B  REGISTER PIO0_2 (rw): I/O configuration for pin PIO0_2/SSEL0/ CT16B0_CAP0
0x4004401C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004401C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004401C C   FIELD 05w01 HYS: Hysteresis
0x4004401C C   FIELD 06w04 RESERVED: Reserved
0x4004401C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004401C C   FIELD 11w21 RESERVED: Reserved
0x40044020 B  REGISTER PIO2_7 (rw): I/O configuration for pin PIO2_7
0x40044020 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044020 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044020 C   FIELD 05w01 HYS: Hysteresis
0x40044020 C   FIELD 06w04 RESERVED: Reserved
0x40044020 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044020 C   FIELD 11w21 RESERVED: Reserved
0x40044024 B  REGISTER PIO2_8 (rw): I/O configuration for pin PIO2_8
0x40044024 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044024 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044024 C   FIELD 05w01 HYS: Hysteresis
0x40044024 C   FIELD 06w04 RESERVED: Reserved
0x40044024 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044024 C   FIELD 11w21 RESERVED: Reserved
0x40044028 B  REGISTER PIO2_1 (rw): I/O configuration for pin PIO2_1/DSR/SCK1
0x40044028 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044028 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044028 C   FIELD 05w01 HYS: Hysteresis
0x40044028 C   FIELD 06w04 RESERVED: Reserved
0x40044028 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044028 C   FIELD 11w21 RESERVED: Reserved
0x4004402C B  REGISTER PIO0_3 (rw): I/O configuration for pin PIO0_3/USB_VBUS
0x4004402C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004402C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004402C C   FIELD 05w01 HYS: Hysteresis
0x4004402C C   FIELD 06w04 RESERVED: Reserved
0x4004402C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004402C C   FIELD 11w21 RESERVED: Reserved
0x40044030 B  REGISTER PIO0_4 (rw): I/O configuration for pin PIO0_4/SCL
0x40044030 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044030 C   FIELD 03w05 RESERVED: Reserved
0x40044030 C   FIELD 08w02 I2CMODE: Selects I2C mode. Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
0x40044030 C   FIELD 10w22 RESERVED: Reserved
0x40044034 B  REGISTER PIO0_5 (rw): I/O configuration for pin PIO0_5/SDA
0x40044034 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044034 C   FIELD 03w05 RESERVED: Reserved
0x40044034 C   FIELD 08w02 I2CMODE: Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
0x40044034 C   FIELD 10w22 RESERVED: Reserved
0x40044038 B  REGISTER PIO1_9 (rw): I/O configuration for pin PIO1_9/CT16B1_MAT0
0x40044038 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044038 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044038 C   FIELD 05w01 HYS: Hysteresis
0x40044038 C   FIELD 06w04 RESERVED: Reserved
0x40044038 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044038 C   FIELD 11w21 RESERVED: Reserved
0x4004403C B  REGISTER PIO3_4 (rw): I/O configuration for pin PIO3_4
0x4004403C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004403C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004403C C   FIELD 05w01 HYS: Hysteresis
0x4004403C C   FIELD 06w04 RESERVED: Reserved
0x4004403C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004403C C   FIELD 11w21 RESERVED: Reserved
0x40044040 B  REGISTER PIO2_4 (rw): I/O configuration for pin PIO2_4
0x40044040 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044040 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044040 C   FIELD 05w01 HYS: Hysteresis
0x40044040 C   FIELD 06w04 RESERVED: Reserved
0x40044040 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044040 C   FIELD 11w21 RESERVED: Reserved
0x40044044 B  REGISTER PIO2_5 (rw): I/O configuration for pin PIO2_5
0x40044044 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044044 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044044 C   FIELD 05w01 HYS: Hysteresis
0x40044044 C   FIELD 06w04 RESERVED: Reserved
0x40044044 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044044 C   FIELD 11w21 RESERVED: Reserved
0x40044048 B  REGISTER PIO3_5 (rw): I/O configuration for pin PIO3_5
0x40044048 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044048 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044048 C   FIELD 05w01 HYS: Hysteresis
0x40044048 C   FIELD 06w04 RESERVED: Reserved
0x40044048 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044048 C   FIELD 11w21 RESERVED: Reserved
0x4004404C B  REGISTER PIO0_6 (rw): I/O configuration for pin PIO0_6/USB_CONNECT/SCK
0x4004404C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004404C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004404C C   FIELD 05w01 HYS: Hysteresis
0x4004404C C   FIELD 06w04 RESERVED: Reserved
0x4004404C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004404C C   FIELD 11w21 RESERVED: Reserved
0x40044050 B  REGISTER PIO0_7 (rw): I/O configuration for pin PIO0_7/CTS
0x40044050 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044050 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044050 C   FIELD 05w01 HYS: Hysteresis
0x40044050 C   FIELD 06w04 RESERVED: Reserved
0x40044050 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044050 C   FIELD 11w21 RESERVED: Reserved
0x40044054 B  REGISTER PIO2_9 (rw): I/O configuration for pin PIO2_9
0x40044054 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044054 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044054 C   FIELD 05w01 HYS: Hysteresis
0x40044054 C   FIELD 06w04 RESERVED: Reserved
0x40044054 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044054 C   FIELD 11w21 RESERVED: Reserved
0x40044058 B  REGISTER PIO2_10 (rw): I/O configuration for pin PIO2_10
0x40044058 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044058 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044058 C   FIELD 05w01 HYS: Hysteresis
0x40044058 C   FIELD 06w04 RESERVED: Reserved
0x40044058 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044058 C   FIELD 11w21 RESERVED: Reserved
0x4004405C B  REGISTER PIO2_2 (rw): I/O configuration for pin PIO2_2/DCD/MISO1
0x4004405C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004405C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004405C C   FIELD 05w01 HYS: Hysteresis
0x4004405C C   FIELD 06w04 RESERVED: Reserved
0x4004405C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004405C C   FIELD 11w21 RESERVED: Reserved
0x40044060 B  REGISTER PIO0_8 (rw): I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0
0x40044060 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044060 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044060 C   FIELD 05w01 HYS: Hysteresis
0x40044060 C   FIELD 06w04 RESERVED: Reserved
0x40044060 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044060 C   FIELD 11w21 RESERVED: Reserved
0x40044064 B  REGISTER PIO0_9 (rw): I/O configuration for pin PIO0_9/MOSI0/ CT16B0_MAT1/SWO
0x40044064 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044064 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044064 C   FIELD 05w01 HYS: Hysteresis
0x40044064 C   FIELD 06w04 RESERVED: Reserved
0x40044064 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044064 C   FIELD 11w21 RESERVED: Reserved
0x40044068 B  REGISTER SWCLK_PIO0_10 (rw): I/O configuration for pin SWCLK/PIO0_10/ SCK/CT16B0_MAT2
0x40044068 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044068 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044068 C   FIELD 05w01 HYS: Hysteresis
0x40044068 C   FIELD 06w04 RESERVED: Reserved
0x40044068 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044068 C   FIELD 11w21 RESERVED: Reserved
0x4004406C B  REGISTER PIO1_10 (rw): I/O configuration for pin PIO1_10/AD6/ CT16B1_MAT1
0x4004406C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004406C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004406C C   FIELD 05w01 HYS: Hysteresis
0x4004406C C   FIELD 06w01 RESERVED: Reserved
0x4004406C C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x4004406C C   FIELD 08w02 RESERVED: Reserved
0x4004406C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004406C C   FIELD 11w21 RESERVED: Reserved
0x40044070 B  REGISTER PIO2_11 (rw): I/O configuration for pin PIO2_11/SCK
0x40044070 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044070 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044070 C   FIELD 05w01 HYS: Hysteresis
0x40044070 C   FIELD 06w04 RESERVED: Reserved
0x40044070 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044070 C   FIELD 11w21 RESERVED: Reserved
0x40044074 B  REGISTER R_PIO0_11 (rw): I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3
0x40044074 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044074 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044074 C   FIELD 05w01 HYS: Hysteresis
0x40044074 C   FIELD 06w01 RESERVED: Reserved
0x40044074 C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x40044074 C   FIELD 08w02 RESERVED: Reserved
0x40044074 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044074 C   FIELD 11w21 RESERVED: Reserved
0x40044078 B  REGISTER R_PIO1_0 (rw): I/O configuration for pin R/PIO1_0/AD1/ CT32B1_CAP0
0x40044078 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044078 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044078 C   FIELD 05w01 HYS: Hysteresis
0x40044078 C   FIELD 06w01 RESERVED: Reserved
0x40044078 C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x40044078 C   FIELD 08w02 RESERVED: Reserved
0x40044078 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044078 C   FIELD 11w21 RESERVED: Reserved
0x4004407C B  REGISTER R_PIO1_1 (rw): I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0
0x4004407C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004407C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004407C C   FIELD 05w01 HYS: Hysteresis
0x4004407C C   FIELD 06w01 RESERVED: Reserved
0x4004407C C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x4004407C C   FIELD 08w02 RESERVED: Reserved
0x4004407C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004407C C   FIELD 11w21 RESERVED: Reserved
0x40044080 B  REGISTER R_PIO1_2 (rw): I/O configuration for pin R/PIO1_2/AD3/ CT32B1_MAT1
0x40044080 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044080 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044080 C   FIELD 05w01 HYS: Hysteresis
0x40044080 C   FIELD 06w01 RESERVED: Reserved
0x40044080 C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x40044080 C   FIELD 08w02 RESERVED: Reserved
0x40044080 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044080 C   FIELD 11w21 RESERVED: Reserved
0x40044084 B  REGISTER PIO3_0 (rw): I/O configuration for pin PIO3_0/DTR
0x40044084 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044084 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044084 C   FIELD 05w01 HYS: Hysteresis
0x40044084 C   FIELD 06w04 RESERVED: Reserved
0x40044084 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044084 C   FIELD 11w21 RESERVED: Reserved
0x40044088 B  REGISTER PIO3_1 (rw): I/O configuration for pin PIO3_1/DSR
0x40044088 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044088 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044088 C   FIELD 05w01 HYS: Hysteresis
0x40044088 C   FIELD 06w04 RESERVED: Reserved
0x40044088 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044088 C   FIELD 11w21 RESERVED: Reserved
0x4004408C B  REGISTER PIO2_3 (rw): I/O configuration for pin PIO2_3/RI/MOSI1
0x4004408C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004408C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004408C C   FIELD 05w01 HYS: Hysteresis
0x4004408C C   FIELD 06w04 RESERVED: Reserved
0x4004408C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004408C C   FIELD 11w21 RESERVED: Reserved
0x40044090 B  REGISTER SWDIO_PIO1_3 (rw): I/O configuration for pin SWDIO/PIO1_3/AD4/ CT32B1_MAT2
0x40044090 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044090 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044090 C   FIELD 05w01 HYS: Hysteresis
0x40044090 C   FIELD 06w01 RESERVED: Reserved
0x40044090 C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x40044090 C   FIELD 08w02 RESERVED: Reserved
0x40044090 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044090 C   FIELD 11w21 RESERVED: Reserved
0x40044094 B  REGISTER PIO1_4 (rw): I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3
0x40044094 C   FIELD 00w03 FUNC: Selects pin function. This pin functions as WAKEUP pin if the LPC13xx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
0x40044094 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044094 C   FIELD 05w01 HYS: Hysteresis
0x40044094 C   FIELD 06w01 RESERVED: Reserved
0x40044094 C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x40044094 C   FIELD 08w02 RESERVED: Reserved
0x40044094 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044094 C   FIELD 11w21 RESERVED: Reserved
0x40044098 B  REGISTER PIO1_11 (rw): I/O configuration for pin PIO1_11/AD7
0x40044098 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x40044098 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x40044098 C   FIELD 05w01 HYS: Hysteresis
0x40044098 C   FIELD 06w01 RESERVED: Reserved
0x40044098 C   FIELD 07w01 ADMODE: Selects Analog/Digital mode
0x40044098 C   FIELD 08w02 RESERVED: Reserved
0x40044098 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x40044098 C   FIELD 11w21 RESERVED: Reserved
0x4004409C B  REGISTER PIO3_2 (rw): I/O configuration for pin PIO3_2/DCD
0x4004409C C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x4004409C C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x4004409C C   FIELD 05w01 HYS: Hysteresis
0x4004409C C   FIELD 06w04 RESERVED: Reserved
0x4004409C C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x4004409C C   FIELD 11w21 RESERVED: Reserved
0x400440A0 B  REGISTER PIO1_5 (rw): I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0
0x400440A0 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x400440A0 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x400440A0 C   FIELD 05w01 HYS: Hysteresis
0x400440A0 C   FIELD 06w04 RESERVED: Reserved
0x400440A0 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x400440A0 C   FIELD 11w21 RESERVED: Reserved
0x400440A4 B  REGISTER PIO1_6 (rw): I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0
0x400440A4 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x400440A4 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x400440A4 C   FIELD 05w01 HYS: Hysteresis
0x400440A4 C   FIELD 06w04 RESERVED: Reserved
0x400440A4 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x400440A4 C   FIELD 11w21 RESERVED: Reserved
0x400440A8 B  REGISTER PIO1_7 (rw): I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1
0x400440A8 C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x400440A8 C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x400440A8 C   FIELD 05w01 HYS: Hysteresis
0x400440A8 C   FIELD 06w04 RESERVED: Reserved
0x400440A8 C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x400440A8 C   FIELD 11w21 RESERVED: Reserved
0x400440AC B  REGISTER PIO3_3 (rw): I/O configuration for pin PIO3_3/RI
0x400440AC C   FIELD 00w03 FUNC: Selects pin function. All other values are reserved.
0x400440AC C   FIELD 03w02 MODE: Selects function mode (on-chip pull-up/pull-down resistor control)
0x400440AC C   FIELD 05w01 HYS: Hysteresis
0x400440AC C   FIELD 06w04 RESERVED: Reserved
0x400440AC C   FIELD 10w01 OD: Selects pseudo open-drain mode.
0x400440AC C   FIELD 11w21 RESERVED: Reserved
0x400440B0 B  REGISTER SCK0_LOC (rw): SCK0 pin location register
0x400440B0 C   FIELD 00w02 SCKLOC: Selects pin location for SCK0 pin.
0x400440B0 C   FIELD 02w30 RESERVED: Reserved
0x400440B4 B  REGISTER DSR_LOC (rw): DSR pin location select register
0x400440B4 C   FIELD 00w02 DSRLOC: Selects pin location for DSR0 pin (this register is only used for parts LPC1311/01 and LPC1313/01).
0x400440B4 C   FIELD 02w30 RESERVED: Reserved.
0x400440B8 B  REGISTER DCD_LOC (rw): DCD pin location select register
0x400440B8 C   FIELD 00w02 DCDLOC: Selects pin location for DCD pin (this register is only used for parts LPC1311/01 and LPC1313/01).
0x400440B8 C   FIELD 02w30 RESERVED: Reserved.
0x400440BC B  REGISTER RI_LOC (rw): RI pin location register
0x400440BC C   FIELD 00w02 RILOC: Selects pin location for RI pin (this register is only used for parts LPC1311/01 and LPC1313/01)
0x400440BC C   FIELD 02w30 RESERVED: Reserved.
0x40048000 A PERIPHERAL SYSCON
0x40048000 B  REGISTER SYSMEMREMAP (rw): System memory remap
0x40048000 C   FIELD 00w02 MAP: System memory remap
0x40048000 C   FIELD 02w30 RESERVED: Reserved
0x40048004 B  REGISTER PRESETCTRL (rw): Peripheral reset control
0x40048004 C   FIELD 00w01 SSP0_RST_N: SSP0 reset control
0x40048004 C   FIELD 01w01 I2C_RST_N: I2C reset control
0x40048004 C   FIELD 02w01 SSP1_RST_N: SPISP1 reset control
0x40048004 C   FIELD 23w09 RESERVED: Reserved
0x40048008 B  REGISTER SYSPLLCTRL (rw): System PLL control
0x40048008 C   FIELD 00w05 MSEL: Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.
0x40048008 C   FIELD 05w02 PSEL: Post divider ratio P. The division ratio is 2 x P.
0x40048008 C   FIELD 07w25 RESERVED: Reserved. Do not write ones to reserved bits.
0x4004800C B  REGISTER SYSPLLSTAT (ro): System PLL status
0x4004800C C   FIELD 00w01 LOCK: PLL lock status
0x4004800C C   FIELD 01w31 RESERVED: Reserved
0x40048010 B  REGISTER USBPLLCTRL (rw): USB PLL control
0x40048010 C   FIELD 00w05 MSEL: Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.
0x40048010 C   FIELD 05w02 PSEL: Post divider ratio P. The division ratio is 2 x P.
0x40048010 C   FIELD 07w25 RESERVED: Reserved. Do not write ones to reserved bits.
0x40048014 B  REGISTER USBPLLSTAT (ro): USB PLL status
0x40048014 C   FIELD 00w01 LOCK: PLL lock status
0x40048014 C   FIELD 01w31 RESERVED: Reserved
0x40048020 B  REGISTER SYSOSCCTRL (rw): System oscillator control
0x40048020 C   FIELD 00w01 BYPASS: Bypass system oscillator
0x40048020 C   FIELD 01w01 FREQRANGE: Determines frequency range for Low-power oscillator.
0x40048020 C   FIELD 02w30 RESERVED: Reserved
0x40048024 B  REGISTER WDTOSCCTRL (rw): Watchdog oscillator control
0x40048024 C   FIELD 00w05 DIVSEL: Select divider for Fclkana. wdt_osc_clk = Fclkana (2 x (1 + DIVSEL)). 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64
0x40048024 C   FIELD 05w04 FREQSEL: Select watchdog oscillator analog output frequency (Fclkana).
0x40048024 C   FIELD 09w23 RESERVED: Reserved
0x40048028 B  REGISTER IRCCTRL (rw): IRC control
0x40048028 C   FIELD 00w08 TRIM: Trim value
0x40048028 C   FIELD 08w24 RESERVED: Reserved
0x40048030 B  REGISTER SYSRESSTAT (ro): System reset status register
0x40048030 C   FIELD 00w01 POR: POR reset status
0x40048030 C   FIELD 01w01 EXTRST: Status of the external RESET pin
0x40048030 C   FIELD 02w01 WDT: Status of the Watchdog reset
0x40048030 C   FIELD 03w01 BOD: Status of the Brown-out detect reset
0x40048030 C   FIELD 04w01 SYSRST: Status of the software system reset. The ARM software reset has the same effect as the hardware reset using the RESET pin.
0x40048030 C   FIELD 05w27 RESERVED: Reserved
0x40048040 B  REGISTER SYSPLLCLKSEL (rw): System PLL clock source select
0x40048040 C   FIELD 00w02 SEL: System PLL clock source
0x40048040 C   FIELD 02w30 RESERVED: Reserved
0x40048044 B  REGISTER SYSPLLCLKUEN (rw): System PLL clock source update enable
0x40048044 C   FIELD 00w01 ENA: Enable system PLL clock source update
0x40048044 C   FIELD 01w31 RESERVED: Reserved
0x40048048 B  REGISTER USBPLLCLKSEL (rw): USB PLL clock source select
0x40048048 C   FIELD 00w02 SEL: USB PLL clock source
0x40048048 C   FIELD 02w30 RESERVED: Reserved
0x4004804C B  REGISTER USBPLLCLKUEN (rw): USB PLL clock source update enable
0x4004804C C   FIELD 00w01 ENA: Enable USB PLL clock source update
0x4004804C C   FIELD 01w31 RESERVED: Reserved
0x40048070 B  REGISTER MAINCLKSEL (rw): Main clock source select
0x40048070 C   FIELD 00w02 SEL: Clock source for main clock
0x40048070 C   FIELD 02w30 RESERVED: Reserved
0x40048074 B  REGISTER MAINCLKUEN (rw): Main clock source update enable
0x40048074 C   FIELD 00w01 ENA: Enable main clock source update
0x40048074 C   FIELD 01w31 RESERVED: Reserved
0x40048078 B  REGISTER SYSAHBCLKDIV (rw): System AHB clock divider
0x40048078 C   FIELD 00w08 DIV: System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
0x40048078 C   FIELD 08w24 RESERVED: Reserved
0x40048080 B  REGISTER SYSAHBCLKCTRL (rw): System AHB clock control
0x40048080 C   FIELD 00w01 SYS: Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M3 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.
0x40048080 C   FIELD 01w01 ROM: Enables clock for ROM.
0x40048080 C   FIELD 02w01 RAM: Enables clock for RAM.
0x40048080 C   FIELD 03w01 FLASHREG: Enables clock for flash register interface.
0x40048080 C   FIELD 04w01 FLASHARRAY: Enables clock for flash array access.
0x40048080 C   FIELD 05w01 I2C: Enables clock for I2C.
0x40048080 C   FIELD 06w01 GPIO: Enables clock for GPIO.
0x40048080 C   FIELD 07w01 CT16B0: Enables clock for 16-bit counter/timer 0.
0x40048080 C   FIELD 08w01 CT16B1: Enables clock for 16-bit counter/timer 1.
0x40048080 C   FIELD 09w01 CT32B0: Enables clock for 32-bit counter/timer 0.
0x40048080 C   FIELD 10w01 CT32B1: Enables clock for 32-bit counter/timer 1.
0x40048080 C   FIELD 11w01 SSP: Enables clock for SSP.
0x40048080 C   FIELD 12w01 UART: Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled.
0x40048080 C   FIELD 13w01 ADC: Enables clock for ADC.
0x40048080 C   FIELD 14w01 USB_REG: Enables clock for USB_REG.
0x40048080 C   FIELD 15w01 WDT: Enables clock for WDT.
0x40048080 C   FIELD 16w01 IOCON: Enables clock for IO configuration block.
0x40048080 C   FIELD 17w15 RESERVED: Reserved
0x40048080 C   FIELD 18w01 SSP1: Enables clock for SPISP1.
0x40048080 C   FIELD 19w13 RESERVED: Reserved
0x40048094 B  REGISTER SSP0CLKDIV (rw): SSP clock divder
0x40048094 C   FIELD 00w08 DIV: SSP_PCLK clock divider values. 0: Disable SSP0_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x40048094 C   FIELD 08w24 RESERVED: Reserved
0x40048098 B  REGISTER UARTCLKDIV (rw): UART clock divder
0x40048098 C   FIELD 00w08 DIV: UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x40048098 C   FIELD 08w24 RESERVED: Reserved
0x4004809C B  REGISTER SSP1CLKDIV (rw): SPISP1 clock divder
0x4004809C C   FIELD 00w08 DIV: SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x4004809C C   FIELD 08w24 RESERVED: Reserved
0x400480AC B  REGISTER TRACECLKDIV (rw): ARM trace clock divider
0x400480AC C   FIELD 00w08 DIV: ARM trace clock divider values. 0: Disable TRACE_CLK. 1: Divide by 1. to 255: Divide by 255.
0x400480AC C   FIELD 08w24 RESERVED: Reserved
0x400480B0 B  REGISTER SYSTICKCLKDIV (rw): SYSTICK clock divder
0x400480B0 C   FIELD 00w08 DIV: SYSTICK clock divider values. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255.
0x400480B0 C   FIELD 08w24 RESERVED: Reserved
0x400480C0 B  REGISTER USBCLKSEL (rw): USB clock source select
0x400480C0 C   FIELD 00w02 SEL: USB clock source
0x400480C0 C   FIELD 02w30 RESERVED: Reserved
0x400480C4 B  REGISTER USBCLKUEN (rw): USB clock source update enable
0x400480C4 C   FIELD 00w01 ENA: Enable USB clock source update
0x400480C4 C   FIELD 01w31 RESERVED: Reserved
0x400480C8 B  REGISTER USBCLKDIV (rw): USB clock source divider
0x400480C8 C   FIELD 00w08 DIV: USB clock divider values. 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255.
0x400480C8 C   FIELD 08w24 RESERVED: Reserved
0x400480D0 B  REGISTER WDTCLKSEL (rw): WDT clock source select
0x400480D0 C   FIELD 00w02 SEL: WDT clock source
0x400480D0 C   FIELD 02w30 RESERVED: Reserved
0x400480D4 B  REGISTER WDTCLKUEN (rw): WDT clock source update enable
0x400480D4 C   FIELD 00w01 ENA: Enable WDT clock source update
0x400480D4 C   FIELD 01w31 RESERVED: Reserved
0x400480D8 B  REGISTER WDTCLKDIV (rw): WDT clock divider
0x400480D8 C   FIELD 00w08 DIV: WDT clock divider values. 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255.
0x400480D8 C   FIELD 08w24 RESERVED: Reserved
0x400480E0 B  REGISTER CLKOUTCLKSEL (rw): CLKOUT clock source select
0x400480E0 C   FIELD 00w02 SEL: CLKOUT clock source
0x400480E0 C   FIELD 02w30 RESERVED: Reserved
0x400480E4 B  REGISTER CLKOUTUEN (rw): CLKOUT clock source update enable
0x400480E4 C   FIELD 00w01 ENA: Enable CLKOUT clock source update
0x400480E4 C   FIELD 01w31 RESERVED: Reserved
0x400480E8 B  REGISTER CLKOUTDIV (rw): CLKOUT clock divider
0x400480E8 C   FIELD 00w08 DIV: Clock divider values. 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255.
0x400480E8 C   FIELD 08w24 RESERVED: Reserved
0x40048100 B  REGISTER PIOPORCAP0 (ro): POR captured PIO status 0
0x40048100 C   FIELD 00w01 CAPPIO0_0: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 01w01 CAPPIO0_1: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 02w01 CAPPIO0_2: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 03w01 CAPPIO0_3: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 04w01 CAPPIO0_4: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 05w01 CAPPIO0_5: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 06w01 CAPPIO0_6: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 07w01 CAPPIO0_7: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 08w01 CAPPIO0_8: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 09w01 CAPPIO0_9: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 10w01 CAPPIO0_10: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 11w01 CAPPIO0_11: Raw reset status input PIO0_11 to PIO0_0
0x40048100 C   FIELD 12w01 CAPPIO1_0: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 13w01 CAPPIO1_1: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 14w01 CAPPIO1_2: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 15w01 CAPPIO1_3: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 16w01 CAPPIO1_4: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 17w01 CAPPIO1_5: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 18w01 CAPPIO1_6: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 19w01 CAPPIO1_7: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 20w01 CAPPIO1_8: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 21w01 CAPPIO1_9: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 22w01 CAPPIO1_10: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 23w01 CAPPIO1_11: Raw reset status input PIO1_11 to PIO1_0
0x40048100 C   FIELD 24w01 CAPPIO2_0: Raw reset status input PIO2_7 to PIO2_0
0x40048100 C   FIELD 25w01 CAPPIO2_1: Raw reset status input PIO2_7 to PIO2_0
0x40048100 C   FIELD 26w01 CAPPIO2_2: Raw reset status input PIO2_7 to PIO2_0
0x40048100 C   FIELD 27w01 CAPPIO2_3: Raw reset status input PIO2_7 to PIO2_0
0x40048100 C   FIELD 28w01 CAPPIO2_4: Raw reset status input PIO2_7 to PIO2_0
0x40048100 C   FIELD 29w01 CAPPIO2_5: Raw reset status input PIO2_7 to PIO2_0
0x40048100 C   FIELD 30w01 CAPPIO2_6: Raw reset status input PIO2_7 to PIO2_0
0x40048100 C   FIELD 31w01 CAPPIO2_7: Raw reset status input PIO2_7 to PIO2_0
0x40048104 B  REGISTER PIOPORCAP1 (ro): POR captured PIO status 1
0x40048104 C   FIELD 00w01 CAPPIO2_8: Raw reset status input PIO2_8
0x40048104 C   FIELD 01w01 CAPPIO2_9: Raw reset status input PIO2_9
0x40048104 C   FIELD 02w01 CAPPIO2_10: Raw reset status input PIO2_10
0x40048104 C   FIELD 03w01 CAPPIO2_11: Raw reset status input PIO2_11
0x40048104 C   FIELD 04w01 CAPPIO3_0: Raw reset status input PIO3_0
0x40048104 C   FIELD 05w01 CAPPIO3_1: Raw reset status input PIO3_1
0x40048104 C   FIELD 06w01 CAPPIO3_2: Raw reset status input PIO3_2
0x40048104 C   FIELD 07w01 CAPPIO3_3: Raw reset status input PIO3_3
0x40048104 C   FIELD 08w01 CAPPIO3_4: Raw reset status input PIO3_4
0x40048104 C   FIELD 09w01 CAPPIO3_5: Raw reset status input PIO3_5
0x40048104 C   FIELD 10w22 RESERVED: Reserved
0x40048150 B  REGISTER BODCTRL (rw): BOD control
0x40048150 C   FIELD 00w02 BODRSTLEV: BOD reset level. Trip values x/y refer to the LPC1300/LPC1300L series.
0x40048150 C   FIELD 02w02 BODINTVAL: BOD interrupt level. Trip values x/y refer to the LPC1300/LPC1300L series.
0x40048150 C   FIELD 04w01 BODRSTENA: BOD reset enable
0x40048150 C   FIELD 05w27 RESERVED: Reserved
0x40048154 B  REGISTER SYSTCKCAL (rw): System tick counter calibration
0x40048154 C   FIELD 00w26 CAL: System tick timer calibration value
0x40048154 C   FIELD 26w06 RESERVED: Reserved
0x40048200 B  REGISTER STARTAPRP0 (rw): Start logic edge control register 0; bottom 32 interrupts
0x40048200 C   FIELD 00w01 APRPIO0_0: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 01w01 APRPIO0_1: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 02w01 APRPIO0_2: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 03w01 APRPIO0_3: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 04w01 APRPIO0_4: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 05w01 APRPIO0_5: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 06w01 APRPIO0_6: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 07w01 APRPIO0_7: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 08w01 APRPIO0_8: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 09w01 APRPIO0_9: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 10w01 APRPIO0_10: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 11w01 APRPIO0_11: Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 12w01 APRPIO1_0: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 13w01 APRPIO1_1: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 14w01 APRPIO1_2: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 15w01 APRPIO1_3: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 16w01 APRPIO1_4: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 17w01 APRPIO1_5: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 18w01 APRPIO1_6: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 19w01 APRPIO1_7: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 20w01 APRPIO1_8: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 21w01 APRPIO1_9: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 22w01 APRPIO1_10: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 23w01 APRPIO1_11: Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 24w01 APRPIO2_0: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 25w01 APRPIO2_1: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 26w01 APRPIO2_2: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 27w01 APRPIO2_3: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 28w01 APRPIO2_4: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 29w01 APRPIO2_5: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 30w01 APRPIO2_6: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048200 C   FIELD 31w01 APRPIO2_7: Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
0x40048204 B  REGISTER STARTERP0 (rw): Start logic signal enable register 0; bottom 32 interrupts
0x40048204 C   FIELD 00w01 ERPIO0_0: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 01w01 ERPIO0_1: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 02w01 ERPIO0_2: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 03w01 ERPIO0_3: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 04w01 ERPIO0_4: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 05w01 ERPIO0_5: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 06w01 ERPIO0_6: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 07w01 ERPIO0_7: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 08w01 ERPIO0_8: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 09w01 ERPIO0_9: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 10w01 ERPIO0_10: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 11w01 ERPIO0_11: Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 12w01 ERPIO1_0: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 13w01 ERPIO1_1: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 14w01 ERPIO1_2: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 15w01 ERPIO1_3: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 16w01 ERPIO1_4: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 17w01 ERPIO1_5: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 18w01 ERPIO1_6: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 19w01 ERPIO1_7: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 20w01 ERPIO1_8: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 21w01 ERPIO1_9: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 22w01 ERPIO1_10: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 23w01 ERPIO1_11: Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 24w01 ERPIO2_0: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 25w01 ERPIO2_1: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 26w01 ERPIO2_2: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 27w01 ERPIO2_3: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 28w01 ERPIO2_4: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 29w01 ERPIO2_5: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 30w01 ERPIO2_6: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048204 C   FIELD 31w01 ERPIO2_7: Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled.
0x40048208 B  REGISTER STARTRSRP0CLR (wo): Start logic reset register 0; bottom 32 interrupts
0x40048208 C   FIELD 00w01 RSRPIO0_0: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 01w01 RSRPIO0_1: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 02w01 RSRPIO0_2: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 03w01 RSRPIO0_3: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 04w01 RSRPIO0_4: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 05w01 RSRPIO0_5: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 06w01 RSRPIO0_6: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 07w01 RSRPIO0_7: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 08w01 RSRPIO0_8: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 09w01 RSRPIO0_9: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 10w01 RSRPIO0_10: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 11w01 RSRPIO0_11: Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 12w01 RSRPIO1_0: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 13w01 RSRPIO1_1: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 14w01 RSRPIO1_2: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 15w01 RSRPIO1_3: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 16w01 RSRPIO1_4: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 17w01 RSRPIO1_5: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 18w01 RSRPIO1_6: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 19w01 RSRPIO1_7: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 20w01 RSRPIO1_8: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 21w01 RSRPIO1_9: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 22w01 RSRPIO1_10: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 23w01 RSRPIO1_11: Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 24w01 RSRPIO2_0: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 25w01 RSRPIO2_1: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 26w01 RSRPIO2_2: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 27w01 RSRPIO2_3: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 28w01 RSRPIO2_4: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 29w01 RSRPIO2_5: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 30w01 RSRPIO2_6: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x40048208 C   FIELD 31w01 RSRPIO2_7: Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal.
0x4004820C B  REGISTER STARTSRP0 (ro): Start logic status register 0; bottom 32 interrupts
0x4004820C C   FIELD 00w01 SRPIO0_0: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 01w01 SRPIO0_1: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 02w01 SRPIO0_2: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 03w01 SRPIO0_3: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 04w01 SRPIO0_4: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 05w01 SRPIO0_5: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 06w01 SRPIO0_6: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 07w01 SRPIO0_7: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 08w01 SRPIO0_8: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 09w01 SRPIO0_9: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 10w01 SRPIO0_10: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 11w01 SRPIO0_11: Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 12w01 SRPIO1_0: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 13w01 SRPIO1_1: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 14w01 SRPIO1_2: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 15w01 SRPIO1_3: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 16w01 SRPIO1_4: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 17w01 SRPIO1_5: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 18w01 SRPIO1_6: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 19w01 SRPIO1_7: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 20w01 SRPIO1_8: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 21w01 SRPIO1_9: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 22w01 SRPIO1_10: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 23w01 SRPIO1_11: Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 24w01 SRPIO2_0: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 25w01 SRPIO2_1: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 26w01 SRPIO2_2: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 27w01 SRPIO2_3: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 28w01 SRPIO2_4: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 29w01 SRPIO2_5: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 30w01 SRPIO2_6: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x4004820C C   FIELD 31w01 SRPIO2_7: Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending.
0x40048210 B  REGISTER STARTAPRP1 (rw): Start logic edge control register 1; top 8 interrupts
0x40048210 C   FIELD 00w01 APRPIO2_8: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 01w01 APRPIO2_9: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 02w01 APRPIO2_10: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 03w01 APRPIO2_11: Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 04w01 APRPIO3_0: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 05w01 APRPIO3_1: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 06w01 APRPIO3_2: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 07w01 APRPIO3_3: Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge.
0x40048210 C   FIELD 08w24 RESERVED: Reserved
0x40048214 B  REGISTER STARTERP1 (rw): Start logic signal enable register 1; top 8 interrupts
0x40048214 C   FIELD 00w01 ERPIO2_8: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 01w01 ERPIO2_9: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 02w01 ERPIO2_10: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 03w01 ERPIO2_11: Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 04w01 ERPIO3_0: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 05w01 ERPIO3_1: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 06w01 ERPIO3_2: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 07w01 ERPIO3_3: Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
0x40048214 C   FIELD 08w24 RESERVED: Reserved
0x40048218 B  REGISTER STARTRSRP1CLR (wo): Start logic reset register 1; top 8 interrupts
0x40048218 C   FIELD 00w01 RSRPIO2_8: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 01w01 RSRPIO2_9: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 02w01 RSRPIO2_10: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 03w01 RSRPIO2_11: Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 04w01 RSRPIO3_0: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 05w01 RSRPIO3_1: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 06w01 RSRPIO3_2: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 07w01 RSRPIO3_3: Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal.
0x40048218 C   FIELD 08w24 RESERVED: Reserved
0x4004821C B  REGISTER STARTSRP1 (ro): Start logic status register 1; top 8 interrupts
0x4004821C C   FIELD 00w01 SRPIO2_8: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 01w01 SRPIO2_9: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 02w01 SRPIO2_10: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 03w01 SRPIO2_11: Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 04w01 SRPIO3_0: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 05w01 SRPIO3_1: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 06w01 SRPIO3_2: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 07w01 SRPIO3_3: Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending.
0x4004821C C   FIELD 08w24 RESERVED: Reserved
0x40048230 B  REGISTER PDSLEEPCFG (rw): Power-down states in Deep-sleep mode
0x40048230 C   FIELD 00w03 FIXEDVAL0: Reserved. Always write these bits as 111.
0x40048230 C   FIELD 03w01 BOD_PD: BOD power-down control in Deep-sleep mode, see Table 49.
0x40048230 C   FIELD 04w02 FIXEDVAL1: Reserved. Always write these bits as 11.
0x40048230 C   FIELD 06w01 WDTOSC_PD: Watchdog oscillator power control in Deep-sleep mode, see Table 49.
0x40048230 C   FIELD 07w05 FIXEDVAL2: Reserved. Always write these bits as 11111.
0x40048230 C   FIELD 12w20 RESERVED: Reserved
0x40048234 B  REGISTER PDAWAKECFG (rw): Power-down states after wake-up from Deep-sleep mode
0x40048234 C   FIELD 00w01 IRCOUT_PD: IRC oscillator output wake-up configuration
0x40048234 C   FIELD 01w01 IRC_PD: IRC oscillator power-down wake-up configuration
0x40048234 C   FIELD 02w01 FLASH_PD: Flash wake-up configuration
0x40048234 C   FIELD 03w01 BOD_PD: BOD wake-up configuration
0x40048234 C   FIELD 04w01 ADC_PD: ADC wake-up configuration
0x40048234 C   FIELD 05w01 SYSOSC_PD: System oscillator wake-up configuration
0x40048234 C   FIELD 06w01 WDTOSC_PD: Watchdog oscillator wake-up configuration
0x40048234 C   FIELD 07w01 SYSPLL_PD: System PLL wake-up configuration
0x40048234 C   FIELD 08w01 USBPLL_PD: USB PLL wake-up configuration
0x40048234 C   FIELD 09w01 FIXEDVAL0: Reserved. Always write this bit as 0.
0x40048234 C   FIELD 10w01 USBPAD_PD: USB pad wake-up configuration
0x40048234 C   FIELD 11w01 FIXEDVAL1: Reserved. Always write this bit as 1.
0x40048234 C   FIELD 12w20 RESERVED: Reserved
0x40048238 B  REGISTER PDRUNCFG (rw): Power-down configuration register
0x40048238 C   FIELD 00w01 IRCOUT_PD: IRC oscillator output power-down
0x40048238 C   FIELD 01w01 IRC_PD: IRC oscillator power-down
0x40048238 C   FIELD 02w01 FLASH_PD: Flash power-down
0x40048238 C   FIELD 03w01 BOD_PD: BOD power-down
0x40048238 C   FIELD 04w01 ADC_PD: ADC power-down
0x40048238 C   FIELD 05w01 SYSOSC_PD: System oscillator power-down[1]
0x40048238 C   FIELD 06w01 WDTOSC_PD: Watchdog oscillator power-down
0x40048238 C   FIELD 07w01 SYSPLL_PD: System PLL power-down
0x40048238 C   FIELD 08w01 USBPLL_PD: USB PLL power-down
0x40048238 C   FIELD 09w01 FIXEDVAL0: Reserved. Always write this bit as 0.
0x40048238 C   FIELD 10w01 USBPAD_PD: USB pad power-down configuration
0x40048238 C   FIELD 11w01 FIXEDVAL1: Reserved. Always write this bit as 1.
0x40048238 C   FIELD 12w20 RESERVED: Reserved
0x400483F4 B  REGISTER DEVICE_ID (ro): Device ID
0x400483F4 C   FIELD 00w32 DEVICEID: Device ID for LPC13xx parts: 0x2C42 502B = LPC1311FHN33 0x2C40 102B = LPC1313FHN33 0x2C40 102B = LPC1313FBD48 0x3D01 402B = LPC1342FHN33 0x3D00 002B = LPC1343FHN33 0x3D00 002B = LPC1343FBD48 0x1816 902B = LPC1311FHN33/01 0x1830 102B = LPC1313FHN33/01 0x1830 102B = LPC1313FBD48/01
0x40058000 A PERIPHERAL SSP1
0x40058000 B  REGISTER CR0 (rw): Control Register 0. Selects the serial clock rate, bus type, and data size.
0x40058000 C   FIELD 00w04 DSS: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
0x40058000 C   FIELD 04w02 FRF: Frame Format.
0x40058000 C   FIELD 06w01 CPOL: Clock Out Polarity. This bit is only used in SPI mode.
0x40058000 C   FIELD 07w01 CPHA: Clock Out Phase. This bit is only used in SPI mode.
0x40058000 C   FIELD 08w08 SCR: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR x [SCR+1]).
0x40058000 C   FIELD 16w16 RESERVED: Reserved.
0x40058004 B  REGISTER CR1 (rw): Control Register 1. Selects master/slave and other modes.
0x40058004 C   FIELD 00w01 LBM: Loop Back Mode.
0x40058004 C   FIELD 01w01 SSE: SSP Enable.
0x40058004 C   FIELD 02w01 MS: Master/Slave Mode.This bit can only be written when the SSE bit is 0.
0x40058004 C   FIELD 03w01 SOD: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).
0x40058004 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40058008 B  REGISTER DR (rw): Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
0x40058008 C   FIELD 00w16 DATA: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.
0x40058008 C   FIELD 16w16 RESERVED: Reserved.
0x4005800C B  REGISTER SR (ro): Status Register.
0x4005800C C   FIELD 00w01 TFE: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
0x4005800C C   FIELD 01w01 TNF: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
0x4005800C C   FIELD 02w01 RNE: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
0x4005800C C   FIELD 03w01 RFF: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
0x4005800C C   FIELD 04w01 BSY: Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
0x4005800C C   FIELD 05w27 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40058010 B  REGISTER CPSR (rw): Clock Prescale Register.
0x40058010 C   FIELD 00w08 CPSDVSR: This even value between 2 and 254, by which SSP_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
0x40058010 C   FIELD 08w24 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40058014 B  REGISTER IMSC (rw): Interrupt Mask Set and Clear Register.
0x40058014 C   FIELD 00w01 RORIM: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
0x40058014 C   FIELD 01w01 RTIM: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x40058014 C   FIELD 02w01 RXIM: Software should set this bit to enable interrupt when the Rx FIFO is at least half full.
0x40058014 C   FIELD 03w01 TXIM: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.
0x40058014 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40058018 B  REGISTER RIS (ro): Raw Interrupt Status Register.
0x40058018 C   FIELD 00w01 RORRIS: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
0x40058018 C   FIELD 01w01 RTRIS: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x40058018 C   FIELD 02w01 RXRIS: This bit is 1 if the Rx FIFO is at least half full.
0x40058018 C   FIELD 03w01 TXRIS: This bit is 1 if the Tx FIFO is at least half empty.
0x40058018 C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x4005801C B  REGISTER MIS (ro): Masked Interrupt Status Register.
0x4005801C C   FIELD 00w01 RORMIS: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
0x4005801C C   FIELD 01w01 RTMIS: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x4005801C C   FIELD 02w01 RXMIS: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
0x4005801C C   FIELD 03w01 TXMIS: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
0x4005801C C   FIELD 04w28 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x40058020 B  REGISTER ICR (wo): SSPICR Interrupt Clear Register.
0x40058020 C   FIELD 00w01 RORIC: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.
0x40058020 C   FIELD 01w01 RTIC: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read-bit for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
0x40058020 C   FIELD 02w30 RESERVED: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0x50000000 A PERIPHERAL GPIO0
0x50003FFC B  REGISTER DATA (rw): Port n data register for pins PIOn_0 to PIOn_11
0x50003FFC C   FIELD 00w01 DATA0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 01w01 DATA1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 02w01 DATA2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 03w01 DATA3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 04w01 DATA4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 05w01 DATA5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 06w01 DATA6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 07w01 DATA7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 08w01 DATA8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 09w01 DATA9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 10w01 DATA10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 11w01 DATA11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50003FFC C   FIELD 12w20 RESERVED: Reserved
0x50008000 B  REGISTER DIR (rw): Data direction register for port n
0x50008000 C   FIELD 00w01 IO0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 01w01 IO1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 02w01 IO2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 03w01 IO3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 04w01 IO4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 05w01 IO5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 06w01 IO6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 07w01 IO7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 08w01 IO8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 09w01 IO9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 10w01 IO10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 11w01 IO11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50008000 C   FIELD 12w20 RESERVED: Reserved
0x50008004 B  REGISTER IS (rw): Interrupt sense register for port n
0x50008004 C   FIELD 00w01 ISENSE0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 01w01 ISENSE1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 02w01 ISENSE2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 03w01 ISENSE3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 04w01 ISENSE4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 05w01 ISENSE5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 06w01 ISENSE6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 07w01 ISENSE7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 08w01 ISENSE8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 09w01 ISENSE9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 10w01 ISENSE10: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 11w01 ISENSE11: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50008004 C   FIELD 12w20 RESERVED: Reserved
0x50008008 B  REGISTER IBE (rw): Interrupt both edges register for port n
0x50008008 C   FIELD 00w01 IBE0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 01w01 IBE1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 02w01 IBE2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 03w01 IBE3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 04w01 IBE4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 05w01 IBE5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 06w01 IBE6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 07w01 IBE7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 08w01 IBE8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 09w01 IBE9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 10w01 IBE10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 11w01 IBE11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50008008 C   FIELD 12w20 RESERVED: Reserved
0x5000800C B  REGISTER IEV (rw): Interrupt event register for port n
0x5000800C C   FIELD 00w01 IEV0: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 01w01 IEV1: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 02w01 IEV2: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 03w01 IEV3: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 04w01 IEV4: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 05w01 IEV5: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 06w01 IEV6: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 07w01 IEV7: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 08w01 IEV8: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 09w01 IEV9: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 10w01 IEV10: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 11w01 IEV11: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5000800C C   FIELD 12w20 RESERVED: Reserved
0x50008010 B  REGISTER IE (rw): Interrupt mask register for port n
0x50008010 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50008010 C   FIELD 12w20 RESERVED: Reserved
0x50008014 B  REGISTER RIS (ro): Raw interrupt status register for port n
0x50008014 C   FIELD 00w01 RAWST0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 01w01 RAWST1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 02w01 RAWST2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 03w01 RAWST3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 04w01 RAWST4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 05w01 RAWST5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 06w01 RAWST6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 07w01 RAWST7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 08w01 RAWST8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 09w01 RAWST9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 10w01 RAWST10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 11w01 RAWST11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50008014 C   FIELD 12w20 RESERVED: Reserved
0x50008018 B  REGISTER MIS (ro): Masked interrupt status register for port n
0x50008018 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50008018 C   FIELD 12w20 RESERVED: Reserved
0x5000801C B  REGISTER IC (wo): Interrupt clear register for port n
0x5000801C C   FIELD 00w01 CLR0: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 01w01 CLR1: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 02w01 CLR2: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 03w01 CLR3: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 04w01 CLR4: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 05w01 CLR5: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 06w01 CLR6: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 07w01 CLR7: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 08w01 CLR8: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 09w01 CLR9: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 10w01 CLR10: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 11w01 CLR11: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5000801C C   FIELD 12w20 RESERVED: Reserved
0x50010000 A PERIPHERAL GPIO1
0x50013FFC B  REGISTER DATA (rw): Port n data register for pins PIOn_0 to PIOn_11
0x50013FFC C   FIELD 00w01 DATA0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 01w01 DATA1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 02w01 DATA2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 03w01 DATA3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 04w01 DATA4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 05w01 DATA5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 06w01 DATA6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 07w01 DATA7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 08w01 DATA8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 09w01 DATA9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 10w01 DATA10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 11w01 DATA11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50013FFC C   FIELD 12w20 RESERVED: Reserved
0x50018000 B  REGISTER DIR (rw): Data direction register for port n
0x50018000 C   FIELD 00w01 IO0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 01w01 IO1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 02w01 IO2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 03w01 IO3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 04w01 IO4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 05w01 IO5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 06w01 IO6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 07w01 IO7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 08w01 IO8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 09w01 IO9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 10w01 IO10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 11w01 IO11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50018000 C   FIELD 12w20 RESERVED: Reserved
0x50018004 B  REGISTER IS (rw): Interrupt sense register for port n
0x50018004 C   FIELD 00w01 ISENSE0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 01w01 ISENSE1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 02w01 ISENSE2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 03w01 ISENSE3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 04w01 ISENSE4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 05w01 ISENSE5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 06w01 ISENSE6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 07w01 ISENSE7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 08w01 ISENSE8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 09w01 ISENSE9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 10w01 ISENSE10: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 11w01 ISENSE11: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50018004 C   FIELD 12w20 RESERVED: Reserved
0x50018008 B  REGISTER IBE (rw): Interrupt both edges register for port n
0x50018008 C   FIELD 00w01 IBE0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 01w01 IBE1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 02w01 IBE2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 03w01 IBE3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 04w01 IBE4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 05w01 IBE5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 06w01 IBE6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 07w01 IBE7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 08w01 IBE8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 09w01 IBE9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 10w01 IBE10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 11w01 IBE11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50018008 C   FIELD 12w20 RESERVED: Reserved
0x5001800C B  REGISTER IEV (rw): Interrupt event register for port n
0x5001800C C   FIELD 00w01 IEV0: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 01w01 IEV1: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 02w01 IEV2: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 03w01 IEV3: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 04w01 IEV4: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 05w01 IEV5: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 06w01 IEV6: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 07w01 IEV7: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 08w01 IEV8: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 09w01 IEV9: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 10w01 IEV10: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 11w01 IEV11: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5001800C C   FIELD 12w20 RESERVED: Reserved
0x50018010 B  REGISTER IE (rw): Interrupt mask register for port n
0x50018010 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50018010 C   FIELD 12w20 RESERVED: Reserved
0x50018014 B  REGISTER RIS (ro): Raw interrupt status register for port n
0x50018014 C   FIELD 00w01 RAWST0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 01w01 RAWST1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 02w01 RAWST2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 03w01 RAWST3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 04w01 RAWST4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 05w01 RAWST5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 06w01 RAWST6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 07w01 RAWST7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 08w01 RAWST8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 09w01 RAWST9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 10w01 RAWST10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 11w01 RAWST11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50018014 C   FIELD 12w20 RESERVED: Reserved
0x50018018 B  REGISTER MIS (ro): Masked interrupt status register for port n
0x50018018 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50018018 C   FIELD 12w20 RESERVED: Reserved
0x5001801C B  REGISTER IC (wo): Interrupt clear register for port n
0x5001801C C   FIELD 00w01 CLR0: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 01w01 CLR1: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 02w01 CLR2: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 03w01 CLR3: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 04w01 CLR4: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 05w01 CLR5: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 06w01 CLR6: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 07w01 CLR7: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 08w01 CLR8: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 09w01 CLR9: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 10w01 CLR10: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 11w01 CLR11: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5001801C C   FIELD 12w20 RESERVED: Reserved
0x50020000 A PERIPHERAL GPIO2
0x50023FFC B  REGISTER DATA (rw): Port n data register for pins PIOn_0 to PIOn_11
0x50023FFC C   FIELD 00w01 DATA0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 01w01 DATA1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 02w01 DATA2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 03w01 DATA3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 04w01 DATA4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 05w01 DATA5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 06w01 DATA6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 07w01 DATA7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 08w01 DATA8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 09w01 DATA9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 10w01 DATA10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 11w01 DATA11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50023FFC C   FIELD 12w20 RESERVED: Reserved
0x50028000 B  REGISTER DIR (rw): Data direction register for port n
0x50028000 C   FIELD 00w01 IO0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 01w01 IO1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 02w01 IO2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 03w01 IO3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 04w01 IO4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 05w01 IO5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 06w01 IO6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 07w01 IO7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 08w01 IO8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 09w01 IO9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 10w01 IO10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 11w01 IO11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50028000 C   FIELD 12w20 RESERVED: Reserved
0x50028004 B  REGISTER IS (rw): Interrupt sense register for port n
0x50028004 C   FIELD 00w01 ISENSE0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 01w01 ISENSE1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 02w01 ISENSE2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 03w01 ISENSE3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 04w01 ISENSE4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 05w01 ISENSE5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 06w01 ISENSE6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 07w01 ISENSE7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 08w01 ISENSE8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 09w01 ISENSE9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 10w01 ISENSE10: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 11w01 ISENSE11: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50028004 C   FIELD 12w20 RESERVED: Reserved
0x50028008 B  REGISTER IBE (rw): Interrupt both edges register for port n
0x50028008 C   FIELD 00w01 IBE0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 01w01 IBE1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 02w01 IBE2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 03w01 IBE3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 04w01 IBE4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 05w01 IBE5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 06w01 IBE6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 07w01 IBE7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 08w01 IBE8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 09w01 IBE9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 10w01 IBE10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 11w01 IBE11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50028008 C   FIELD 12w20 RESERVED: Reserved
0x5002800C B  REGISTER IEV (rw): Interrupt event register for port n
0x5002800C C   FIELD 00w01 IEV0: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 01w01 IEV1: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 02w01 IEV2: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 03w01 IEV3: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 04w01 IEV4: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 05w01 IEV5: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 06w01 IEV6: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 07w01 IEV7: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 08w01 IEV8: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 09w01 IEV9: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 10w01 IEV10: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 11w01 IEV11: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5002800C C   FIELD 12w20 RESERVED: Reserved
0x50028010 B  REGISTER IE (rw): Interrupt mask register for port n
0x50028010 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50028010 C   FIELD 12w20 RESERVED: Reserved
0x50028014 B  REGISTER RIS (ro): Raw interrupt status register for port n
0x50028014 C   FIELD 00w01 RAWST0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 01w01 RAWST1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 02w01 RAWST2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 03w01 RAWST3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 04w01 RAWST4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 05w01 RAWST5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 06w01 RAWST6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 07w01 RAWST7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 08w01 RAWST8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 09w01 RAWST9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 10w01 RAWST10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 11w01 RAWST11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50028014 C   FIELD 12w20 RESERVED: Reserved
0x50028018 B  REGISTER MIS (ro): Masked interrupt status register for port n
0x50028018 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50028018 C   FIELD 12w20 RESERVED: Reserved
0x5002801C B  REGISTER IC (wo): Interrupt clear register for port n
0x5002801C C   FIELD 00w01 CLR0: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 01w01 CLR1: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 02w01 CLR2: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 03w01 CLR3: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 04w01 CLR4: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 05w01 CLR5: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 06w01 CLR6: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 07w01 CLR7: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 08w01 CLR8: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 09w01 CLR9: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 10w01 CLR10: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 11w01 CLR11: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5002801C C   FIELD 12w20 RESERVED: Reserved
0x50030000 A PERIPHERAL GPIO3
0x50033FFC B  REGISTER DATA (rw): Port n data register for pins PIOn_0 to PIOn_11
0x50033FFC C   FIELD 00w01 DATA0: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 01w01 DATA1: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 02w01 DATA2: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 03w01 DATA3: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 04w01 DATA4: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 05w01 DATA5: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 06w01 DATA6: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 07w01 DATA7: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 08w01 DATA8: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 09w01 DATA9: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 10w01 DATA10: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 11w01 DATA11: Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
0x50033FFC C   FIELD 12w20 RESERVED: Reserved
0x50038000 B  REGISTER DIR (rw): Data direction register for port n
0x50038000 C   FIELD 00w01 IO0: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 01w01 IO1: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 02w01 IO2: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 03w01 IO3: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 04w01 IO4: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 05w01 IO5: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 06w01 IO6: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 07w01 IO7: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 08w01 IO8: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 09w01 IO9: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 10w01 IO10: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 11w01 IO11: Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
0x50038000 C   FIELD 12w20 RESERVED: Reserved
0x50038004 B  REGISTER IS (rw): Interrupt sense register for port n
0x50038004 C   FIELD 00w01 ISENSE0: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 01w01 ISENSE1: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 02w01 ISENSE2: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 03w01 ISENSE3: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 04w01 ISENSE4: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 05w01 ISENSE5: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 06w01 ISENSE6: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 07w01 ISENSE7: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 08w01 ISENSE8: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 09w01 ISENSE9: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 10w01 ISENSE10: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 11w01 ISENSE11: Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
0x50038004 C   FIELD 12w20 RESERVED: Reserved
0x50038008 B  REGISTER IBE (rw): Interrupt both edges register for port n
0x50038008 C   FIELD 00w01 IBE0: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 01w01 IBE1: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 02w01 IBE2: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 03w01 IBE3: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 04w01 IBE4: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 05w01 IBE5: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 06w01 IBE6: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 07w01 IBE7: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 08w01 IBE8: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 09w01 IBE9: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 10w01 IBE10: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 11w01 IBE11: Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
0x50038008 C   FIELD 12w20 RESERVED: Reserved
0x5003800C B  REGISTER IEV (rw): Interrupt event register for port n
0x5003800C C   FIELD 00w01 IEV0: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 01w01 IEV1: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 02w01 IEV2: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 03w01 IEV3: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 04w01 IEV4: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 05w01 IEV5: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 06w01 IEV6: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 07w01 IEV7: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 08w01 IEV8: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 09w01 IEV9: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 10w01 IEV10: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 11w01 IEV11: Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
0x5003800C C   FIELD 12w20 RESERVED: Reserved
0x50038010 B  REGISTER IE (rw): Interrupt mask register for port n
0x50038010 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
0x50038010 C   FIELD 12w20 RESERVED: Reserved
0x50038014 B  REGISTER RIS (ro): Raw interrupt status register for port n
0x50038014 C   FIELD 00w01 RAWST0: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 01w01 RAWST1: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 02w01 RAWST2: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 03w01 RAWST3: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 04w01 RAWST4: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 05w01 RAWST5: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 06w01 RAWST6: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 07w01 RAWST7: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 08w01 RAWST8: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 09w01 RAWST9: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 10w01 RAWST10: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 11w01 RAWST11: Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
0x50038014 C   FIELD 12w20 RESERVED: Reserved
0x50038018 B  REGISTER MIS (ro): Masked interrupt status register for port n
0x50038018 C   FIELD 00w01 MASK0: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 01w01 MASK1: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 02w01 MASK2: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 03w01 MASK3: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 04w01 MASK4: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 05w01 MASK5: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 06w01 MASK6: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 07w01 MASK7: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 08w01 MASK8: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 09w01 MASK9: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 10w01 MASK10: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 11w01 MASK11: Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
0x50038018 C   FIELD 12w20 RESERVED: Reserved
0x5003801C B  REGISTER IC (wo): Interrupt clear register for port n
0x5003801C C   FIELD 00w01 CLR0: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 01w01 CLR1: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 02w01 CLR2: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 03w01 CLR3: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 04w01 CLR4: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 05w01 CLR5: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 06w01 CLR6: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 07w01 CLR7: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 08w01 CLR8: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 09w01 CLR9: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 10w01 CLR10: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 11w01 CLR11: Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
0x5003801C C   FIELD 12w20 RESERVED: Reserved
INTERRUPT 000: PIO0_0 (SYSCON): 
INTERRUPT 001: PIO0_1 (SYSCON): 
INTERRUPT 002: PIO0_2 (SYSCON): 
INTERRUPT 003: PIO0_3 (SYSCON): 
INTERRUPT 004: PIO0_4 (SYSCON): 
INTERRUPT 005: PIO0_5 (SYSCON): 
INTERRUPT 006: PIO0_6 (SYSCON): 
INTERRUPT 007: PIO0_7 (SYSCON): 
INTERRUPT 008: PIO0_8 (SYSCON): 
INTERRUPT 009: PIO0_9 (SYSCON): 
INTERRUPT 010: PIO0_10 (SYSCON): 
INTERRUPT 011: PIO0_11 (SYSCON): 
INTERRUPT 012: PIO1_0 (SYSCON): 
INTERRUPT 013: PIO1_1 (SYSCON): 
INTERRUPT 014: PIO1_2 (SYSCON): 
INTERRUPT 015: PIO1_3 (SYSCON): 
INTERRUPT 016: PIO1_4 (SYSCON): 
INTERRUPT 017: PIO1_5 (SYSCON): 
INTERRUPT 018: PIO1_6 (SYSCON): 
INTERRUPT 019: PIO1_7 (SYSCON): 
INTERRUPT 020: PIO1_8 (SYSCON): 
INTERRUPT 021: PIO1_9 (SYSCON): 
INTERRUPT 022: PIO1_10 (SYSCON): 
INTERRUPT 023: PIO1_11 (SYSCON): 
INTERRUPT 024: PIO2_0 (SYSCON): 
INTERRUPT 025: PIO2_1 (SYSCON): 
INTERRUPT 026: PIO2_2 (SYSCON): 
INTERRUPT 027: PIO2_3 (SYSCON): 
INTERRUPT 028: PIO2_4 (SYSCON): 
INTERRUPT 029: PIO2_5 (SYSCON): 
INTERRUPT 030: PIO2_6 (SYSCON): 
INTERRUPT 031: PIO2_7 (SYSCON): 
INTERRUPT 032: PIO2_8 (SYSCON): 
INTERRUPT 033: PIO2_9 (SYSCON): 
INTERRUPT 034: PIO2_10 (SYSCON): 
INTERRUPT 035: PIO2_11 (SYSCON): 
INTERRUPT 036: PIO3_0 (SYSCON): 
INTERRUPT 037: PIO3_1 (SYSCON): 
INTERRUPT 038: PIO3_2 (SYSCON): 
INTERRUPT 039: PIO3_3 (SYSCON): 
INTERRUPT 040: I2C0 (I2C): 
INTERRUPT 041: CT16B0 (CT16B0): 
INTERRUPT 042: CT16B1 (CT16B1): 
INTERRUPT 043: CT32B0 (CT32B0): 
INTERRUPT 044: CT32B1 (CT32B1): 
INTERRUPT 045: SSP0 (SSP0): 
INTERRUPT 046: UART (UART): 
INTERRUPT 047: USB (USB): 
INTERRUPT 048: USBFIQ (USB): 
INTERRUPT 049: ADC (ADC): 
INTERRUPT 050: WDT (WWDT): 
INTERRUPT 051: BOD (SYSCON): 
INTERRUPT 053: PIO_3 (GPIO3): 
INTERRUPT 054: PIO_2 (GPIO2): 
INTERRUPT 055: PIO_1 (GPIO1): 
INTERRUPT 056: PIO_0 (GPIO0): 
INTERRUPT 057: SSP1 (SSP1):