Error building top.svf

[ghent360]

7.39. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
ERROR: Conflicting init values for signal 1'0 (\eternit.ip_tx_liteethipv4checksum_r_next0 [1] = 1'0 != 1'x).
make: *** [Makefile:19: top.json] Error 1

this is running make top.svf in the fpga/syn folder.

[ghent360]

this is probably an issue with liteeth itself. I re-generated the file and it still fails to compile with yosys.

[rednaz1337]

Yeah I have the same problem.

Edit: Just tried it on another machine, also running Arch Linux, now it works fine. Weird.

Edit 2: now I'm getting

7.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
ERROR: Conflicting init values for signal 1'1 (\eternit.ip_tx_liteethipv4checksum_r_next0 [2] = 1'x != 1'0).
make: *** [Makefile:19: top.json] Fehler 1

[rednaz1337]

Ok, I think this is actually a bug in yosys. When I change

read_verilog ../liteeth_core.v
read_verilog ../udp_panel_writer.v
read_verilog ../ledpanel.v
read_verilog ../pll.v
read_verilog ../phy_io.v
read_verilog ../top.v
synth_ecp5 -retime

to

read_verilog ../liteeth_core.v
read_verilog ../udp_panel_writer.v
read_verilog ../ledpanel.v
read_verilog ../pll.v
read_verilog ../phy_io.v
read_verilog ../top.v

synth_ecp5
synth_ecp5 -retime

it builds this just fine. This also happens when I try to only build LiteEth without this project.