Go this error after changing ip addr

[stanleyseow]

7.35.37.2. Re-integrating ABC results.
ABC RESULTS: AND cells: 1
ABC RESULTS: ANDNOT cells: 1
ABC RESULTS: BUF cells: 304
ABC RESULTS: DFF cells: 160
ABC RESULTS: NAND cells: 2
ABC RESULTS: NOT cells: 17
ABC RESULTS: XNOR cells: 1
ABC RESULTS: XOR cells: 2
ABC RESULTS: internal signals: 22
ABC RESULTS: input signals: 164
ABC RESULTS: output signals: 165
Removing temp directory.

7.36. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
ERROR: Conflicting init values for signal 1'1 (\eternit.ip_tx_liteethipv4checksum_r_next0 [2] = 1'x != 1'0).
Makefile:19: recipe for target 'top.json' failed
make: *** [top.json] Error 1

[stanleyseow]

After adding synth_exp5 to syn.ys , compiled and got this error below ....

Info: Device utilisation:
Info: TRELLIS_SLICE: 54189/12144 446%
Info: TRELLIS_IO: 62/ 197 31%
Info: DCCA: 3/ 56 5%
Info: DP16KD: 4/ 56 7%
Info: MULT18X18D: 0/ 28 0%
Info: ALU54B: 0/ 14 0%
Info: EHXPLLL: 1/ 2 50%
Info: EXTREFB: 0/ 1 0%
Info: DCUA: 0/ 1 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 11/ 128 8%
Info: SIOLOGIC: 0/ 69 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 8 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%

Info: Placed 74 cells based on constraints.
ERROR: Unable to place cell 'genblk1[2].panel_inst.video_mem_g.0.174.0$DPRAM0_SLICE', no BELs remaining to implement cell type 'TRELLIS_SLICE'
0 warnings, 1 error
Makefile:22: recipe for target 'top.config' failed
make: *** [top.config] Error 255

[ponty]

I got the same:

Info: Device utilisation:
Info:          TRELLIS_SLICE: 54612/12144   449%

I replaced 6 with 1 in for (panel_index = 0; panel_index < 6;, it can be built now at least.

Info: Device utilisation:
Info:          TRELLIS_SLICE: 11539/12144    95%