From 3c0e0921d8eff3c350d8c0c7b1fecee0c48bf87f Mon Sep 17 00:00:00 2001 From: Tao Lyu Date: Thu, 26 Sep 2024 10:01:47 +0200 Subject: [PATCH] add a reference to memory consistency and cache coherence --- _posts/2023-11-20-system-hw-concepts.markdown | 1 + 1 file changed, 1 insertion(+) diff --git a/_posts/2023-11-20-system-hw-concepts.markdown b/_posts/2023-11-20-system-hw-concepts.markdown index e33b279..175a5f9 100644 --- a/_posts/2023-11-20-system-hw-concepts.markdown +++ b/_posts/2023-11-20-system-hw-concepts.markdown @@ -297,6 +297,7 @@ https://www.intel.com/content/www/us/en/developer/articles/technical/memory-in-d - [2] [x86-TSO: A Rigorous and Usable Programmer’s Model for x86 Multiprocessors](https://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf) - [3] [A Tutorial Introduction to the ARM and POWER Relaxed Memory Models](https://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf) - [4] [A Formal Model of Linux-Kernel Memory Ordering](https://mirrors.edge.kernel.org/pub/linux/kernel/people/paulmck/LWNLinuxMM/) + - [5] [A Primer on Memory Consistency and Cache Coherence](https://course.ece.cmu.edu/~ece847c/S15/lib/exe/fetch.php?media=part2_2_sorin12.pdf#MC_Sorin-2_Ch02.indd%3Achapter%202) # Performance