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rtw8821c.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2018-2019 Realtek Corporation
*/
#include "main.h"
#include "coex.h"
#include "fw.h"
#include "tx.h"
#include "rx.h"
#include "phy.h"
#include "rtw8821c.h"
#include "rtw8821c_table.h"
#include "mac.h"
#include "reg.h"
#include "debug.h"
#include "bf.h"
#include "regd.h"
static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
-20, -24, -28, -31, -34, -37, -40, -44};
static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
struct rtw8821c_efuse *map)
{
ether_addr_copy(efuse->addr, map->e.mac_addr);
}
static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse,
struct rtw8821c_efuse *map)
{
ether_addr_copy(efuse->addr, map->u.mac_addr);
}
static void rtw8821cs_efuse_parsing(struct rtw_efuse *efuse,
struct rtw8821c_efuse *map)
{
ether_addr_copy(efuse->addr, map->s.mac_addr);
}
enum rtw8821ce_rf_set {
SWITCH_TO_BTG,
SWITCH_TO_WLG,
SWITCH_TO_WLA,
SWITCH_TO_BT,
};
static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
{
struct rtw_hal *hal = &rtwdev->hal;
struct rtw_efuse *efuse = &rtwdev->efuse;
struct rtw8821c_efuse *map;
int i;
map = (struct rtw8821c_efuse *)log_map;
efuse->rfe_option = map->rfe_option & 0x1f;
efuse->rfe_option_full = map->rfe_option;
efuse->rf_board_option = map->rf_board_option;
efuse->crystal_cap = map->xtal_k;
efuse->pa_type_2g = map->pa_type;
efuse->pa_type_5g = map->pa_type;
efuse->lna_type_2g = map->lna_type_2g[0];
efuse->lna_type_5g = map->lna_type_5g[0];
efuse->channel_plan = map->channel_plan;
efuse->country_code[0] = map->country_code[0];
efuse->country_code[1] = map->country_code[1];
efuse->bt_setting = map->rf_bt_setting;
efuse->regd = map->rf_board_option & 0x7;
efuse->thermal_meter[0] = map->thermal_meter;
efuse->thermal_meter_k = map->thermal_meter;
efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0;
switch (efuse->rfe_option) {
case 0x2:
case 0x4:
case 0x7:
case 0xa:
case 0xc:
case 0xf:
hal->rfe_btg = true;
break;
}
for (i = 0; i < 4; i++)
efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
switch (rtw_hci_type(rtwdev)) {
case RTW_HCI_TYPE_PCIE:
rtw8821ce_efuse_parsing(efuse, map);
break;
case RTW_HCI_TYPE_USB:
rtw8821cu_efuse_parsing(efuse, map);
break;
case RTW_HCI_TYPE_SDIO:
rtw8821cs_efuse_parsing(efuse, map);
break;
default:
/* unsupported now */
return -ENOTSUPP;
}
return 0;
}
static const u32 rtw8821c_txscale_tbl[] = {
0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
};
static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
{
u8 i = 0;
u32 swing, table_value;
swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
table_value = rtw8821c_txscale_tbl[i];
if (swing == table_value)
break;
}
return i;
}
static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
dm_info->default_ofdm_index = 24;
else
dm_info->default_ofdm_index = swing_idx;
ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
dm_info->delta_power_index[RF_PATH_A] = 0;
dm_info->delta_power_index_last[RF_PATH_A] = 0;
dm_info->pwr_trk_triggered = false;
dm_info->pwr_trk_init_trigger = true;
dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
}
static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
{
rtw_bf_phy_init(rtwdev);
/* Grouping bitmap parameters */
rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
}
static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
{
struct rtw_hal *hal = &rtwdev->hal;
u8 crystal_cap, val;
/* power on BB/RF domain */
val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
val |= BIT_FEN_PCIEA;
rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
/* toggle BB reset */
val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
rtw_write8(rtwdev, REG_RF_CTRL,
BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
usleep_range(10, 11);
rtw_write8(rtwdev, REG_WLRF1 + 3,
BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
usleep_range(10, 11);
/* pre init before header files config */
rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_phy_load_tables(rtwdev);
crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
/* post init after header files config */
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
rtw_phy_init(rtwdev);
rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
rtw8821c_pwrtrack_init(rtwdev);
rtw8821c_phy_bf_init(rtwdev);
}
static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
{
u32 value32;
u16 pre_txcnt;
/* protocol configuration */
rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
(WLAN_MAX_AGG_PKT_LIMIT << 16) |
(WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
/* EDCA configuration */
rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
rtw_write16(rtwdev, REG_TXPAUSE, 0);
rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
/* Set beacon cotnrol - enable TSF and other related functions */
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
/* Set send beacon related registers */
rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
/* WMAC configuration */
rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
BIT_DIS_CHK_VHTSIGB_CRC);
rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
return 0;
}
static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
{
u8 ldo_pwr;
ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
}
static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
{
u32 reg;
rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
reg = rtw_read32(rtwdev, REG_RFECTL);
switch (rf_set) {
case SWITCH_TO_BTG:
reg |= B_BTG_SWITCH;
reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH |
B_WLA_SWITCH);
rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
break;
case SWITCH_TO_WLG:
reg |= B_WL_SWITCH | B_WLG_SWITCH;
reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH);
rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
break;
case SWITCH_TO_WLA:
reg |= B_WL_SWITCH | B_WLA_SWITCH;
reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH);
break;
case SWITCH_TO_BT:
default:
break;
}
rtw_write32(rtwdev, REG_RFECTL, reg);
}
static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
{
struct rtw_hal *hal = &rtwdev->hal;
u32 rf_reg18;
rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
RF18_BW_MASK);
rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
rf_reg18 |= (channel & RF18_CHANNEL_MASK);
if (channel >= 100 && channel <= 140)
rf_reg18 |= RF18_RFSI_GE;
else if (channel > 140)
rf_reg18 |= RF18_RFSI_GT;
switch (bw) {
case RTW_CHANNEL_WIDTH_5:
case RTW_CHANNEL_WIDTH_10:
case RTW_CHANNEL_WIDTH_20:
default:
rf_reg18 |= RF18_BW_20M;
break;
case RTW_CHANNEL_WIDTH_40:
rf_reg18 |= RF18_BW_40M;
break;
case RTW_CHANNEL_WIDTH_80:
rf_reg18 |= RF18_BW_80M;
break;
}
if (channel <= 14) {
if (hal->rfe_btg)
rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
else
rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
} else {
rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
}
rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
}
static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
{
if (bw == RTW_CHANNEL_WIDTH_40) {
/* RX DFIR for BW40 */
rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
} else if (bw == RTW_CHANNEL_WIDTH_80) {
/* RX DFIR for BW80 */
rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
} else {
/* RX DFIR for BW20, BW10 and BW5 */
rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
}
}
static void rtw8821c_cck_tx_filter_srrc(struct rtw_dev *rtwdev, u8 channel, u8 bw)
{
struct rtw_hal *hal = &rtwdev->hal;
if (channel == 14) {
rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
} else if (channel == 13 ||
(channel == 11 && bw == RTW_CHANNEL_WIDTH_40)) {
rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe);
rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810);
rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
} else {
rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
hal->ch_param[0]);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
hal->ch_param[1] & MASKLWORD);
rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
hal->ch_param[2]);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
}
}
static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
u8 primary_ch_idx)
{
struct rtw_hal *hal = &rtwdev->hal;
u32 val32;
if (channel <= 14) {
rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
if (rtw_regd_srrc(rtwdev)) {
rtw8821c_cck_tx_filter_srrc(rtwdev, channel, bw);
goto set_bw;
}
/* CCK TX filter parameters for default case */
if (channel == 14) {
rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
} else {
rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
hal->ch_param[0]);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
hal->ch_param[1] & MASKLWORD);
rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
hal->ch_param[2]);
}
} else if (channel > 35) {
rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
if (channel >= 36 && channel <= 64)
rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
else if (channel >= 100 && channel <= 144)
rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
else if (channel >= 149)
rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
if (channel >= 36 && channel <= 48)
rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
else if (channel >= 52 && channel <= 64)
rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
else if (channel >= 100 && channel <= 116)
rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
else if (channel >= 118 && channel <= 177)
rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
}
set_bw:
switch (bw) {
case RTW_CHANNEL_WIDTH_20:
default:
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 &= 0xffcffc00;
val32 |= 0x10010000;
rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
break;
case RTW_CHANNEL_WIDTH_40:
if (primary_ch_idx == 1)
rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
else
rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 &= 0xff3ff300;
val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
RTW_CHANNEL_WIDTH_40;
rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
break;
case RTW_CHANNEL_WIDTH_80:
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 &= 0xfcffcf00;
val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
RTW_CHANNEL_WIDTH_80;
rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
break;
case RTW_CHANNEL_WIDTH_5:
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 &= 0xefcefc00;
val32 |= 0x200240;
rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
break;
case RTW_CHANNEL_WIDTH_10:
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 &= 0xefcefc00;
val32 |= 0x300380;
rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
break;
}
}
static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
{
struct rtw_efuse efuse = rtwdev->efuse;
u8 tx_bb_swing;
u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
efuse.tx_bb_swing_setting_5g;
if (tx_bb_swing > 9)
tx_bb_swing = 0;
return swing2setting[(tx_bb_swing / 3)];
}
static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
u8 bw, u8 primary_ch_idx)
{
rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
rtw8821c_get_bb_swing(rtwdev, channel));
rtw8821c_pwrtrack_init(rtwdev);
}
static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
u8 primary_chan_idx)
{
rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
rtw8821c_set_channel_rf(rtwdev, channel, bw);
rtw8821c_set_channel_rxdfir(rtwdev, bw);
}
static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
const s8 *lna_gain_table;
int lna_gain_table_size;
s8 rx_pwr_all = 0;
s8 lna_gain = 0;
if (efuse->rfe_option == 0) {
lna_gain_table = lna_gain_table_0;
lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0);
} else {
lna_gain_table = lna_gain_table_1;
lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1);
}
if (lna_idx >= lna_gain_table_size) {
rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
return -120;
}
lna_gain = lna_gain_table[lna_idx];
rx_pwr_all = lna_gain - 2 * vga_idx;
return rx_pwr_all;
}
static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
struct rtw_rx_pkt_stat *pkt_stat)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
s8 rx_power;
u8 lna_idx = 0;
u8 vga_idx = 0;
vga_idx = GET_PHY_STAT_P0_VGA(phy_status);
lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) |
FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status));
rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
pkt_stat->rx_power[RF_PATH_A] = rx_power;
pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
pkt_stat->signal_power = rx_power;
}
static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
struct rtw_rx_pkt_stat *pkt_stat)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 rxsc, bw;
s8 min_rx_power = -120;
if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
else
rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
if (rxsc >= 1 && rxsc <= 8)
bw = RTW_CHANNEL_WIDTH_20;
else if (rxsc >= 9 && rxsc <= 12)
bw = RTW_CHANNEL_WIDTH_40;
else if (rxsc >= 13)
bw = RTW_CHANNEL_WIDTH_80;
else
bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
pkt_stat->bw = bw;
pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
min_rx_power);
}
static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
struct rtw_rx_pkt_stat *pkt_stat)
{
u8 page;
page = *phy_status & 0xf;
switch (page) {
case 0:
query_phy_status_page0(rtwdev, phy_status, pkt_stat);
break;
case 1:
query_phy_status_page1(rtwdev, phy_status, pkt_stat);
break;
default:
rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
return;
}
}
static void
rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path,
u8 rs, u32 *phy_pwr_idx)
{
struct rtw_hal *hal = &rtwdev->hal;
static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
u8 rate, rate_idx, pwr_index, shift;
int j;
for (j = 0; j < rtw_rate_size[rs]; j++) {
rate = rtw_rate_section[rs][j];
pwr_index = hal->tx_pwr_tbl[path][rate];
shift = rate & 0x3;
*phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
rate_idx = rate & 0xfc;
rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
*phy_pwr_idx);
*phy_pwr_idx = 0;
}
}
}
static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
{
struct rtw_hal *hal = &rtwdev->hal;
u32 phy_pwr_idx = 0;
int rs, path;
for (path = 0; path < hal->rf_path_num; path++) {
for (rs = 0; rs < RTW_RATE_SECTION_HT_3S; rs++) {
if (rs == RTW_RATE_SECTION_HT_2S ||
rs == RTW_RATE_SECTION_VHT_2S)
continue;
rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs,
&phy_pwr_idx);
}
}
}
static void rtw8821c_set_ampdu_factor(struct rtw_dev *rtwdev, u8 factor)
{
rtw_write32(rtwdev, REG_AMPDU_MAX_LENGTH, (8192 << factor) - 1);
}
static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 cck_enable;
u32 cck_fa_cnt;
u32 ofdm_fa_cnt;
u32 crc32_cnt;
u32 cca32_cnt;
cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
dm_info->cck_fa_cnt = cck_fa_cnt;
dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
dm_info->total_fa_cnt = ofdm_fa_cnt;
if (cck_enable)
dm_info->total_fa_cnt += cck_fa_cnt;
crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
if (cck_enable) {
cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
}
rtw_write32_set(rtwdev, REG_FAS, BIT(17));
rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
}
static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
{
static int do_iqk_cnt;
struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
u32 rf_reg, iqk_fail_mask;
int counter;
bool reload;
if (rtw_is_assoc(rtwdev))
para.segment_iqk = 1;
rtw_fw_do_iqk(rtwdev, ¶);
for (counter = 0; counter < 300; counter++) {
rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
if (rf_reg == 0xabcde)
break;
msleep(20);
}
rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
rtw_dbg(rtwdev, RTW_DBG_PHY,
"iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
counter, reload, ++do_iqk_cnt, iqk_fail_mask);
}
static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
{
rtw8821c_do_iqk(rtwdev);
}
/* for coex */
static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
{
/* enable TBTT nterrupt */
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
/* BT report packet sample rate */
rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
/* enable BT counter statistics */
rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
/* enable PTA (3-wire function form BT side) */
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
/* enable PTA (tx/rx signal form WiFi side) */
rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
/* wl tx signal to PTA not case EDCCA */
rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
/* GNT_BT=1 while select both */
rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
/* beacon queue always hi-pri */
rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
BCN_PRI_EN);
}
static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
u8 pos_type)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type;
bool polarity_inverse;
u8 regval = 0;
if (switch_status == coex_dm->cur_switch_status)
return;
if (coex_rfe->wlg_at_btg) {
ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
if (coex_rfe->ant_switch_polarity)
pos_type = COEX_SWITCH_TO_WLA;
else
pos_type = COEX_SWITCH_TO_WLG_BT;
}
coex_dm->cur_switch_status = switch_status;
if (coex_rfe->ant_switch_diversity &&
ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
switch (ctrl_type) {
default:
case COEX_SWITCH_CTRL_BY_BBSW:
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
DPDT_CTRL_PIN);
if (pos_type == COEX_SWITCH_TO_WLG_BT) {
if (coex_rfe->rfe_module_type != 0x4 &&
coex_rfe->rfe_module_type != 0x2)
regval = 0x3;
else
regval = (!polarity_inverse ? 0x2 : 0x1);
} else if (pos_type == COEX_SWITCH_TO_WLG) {
regval = (!polarity_inverse ? 0x2 : 0x1);
} else {
regval = (!polarity_inverse ? 0x1 : 0x2);
}
rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
regval);
break;
case COEX_SWITCH_CTRL_BY_PTA:
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
/* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
PTA_CTRL_PIN);
regval = (!polarity_inverse ? 0x2 : 0x1);
rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
regval);
break;
case COEX_SWITCH_CTRL_BY_ANTDIV:
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
ANTDIC_CTRL_PIN);
break;
case COEX_SWITCH_CTRL_BY_MAC:
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
regval = (!polarity_inverse ? 0x0 : 0x1);
rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
regval);
break;
case COEX_SWITCH_CTRL_BY_FW:
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
break;
case COEX_SWITCH_CTRL_BY_BT:
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
break;
}
if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
} else {
rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
}
}
static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
{}
static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
{
rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
}
static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
struct rtw_efuse *efuse = &rtwdev->efuse;
coex_rfe->rfe_module_type = efuse->rfe_option;
coex_rfe->ant_switch_polarity = 0;
coex_rfe->ant_switch_exist = true;
coex_rfe->wlg_at_btg = false;
switch (coex_rfe->rfe_module_type) {
case 0:
case 8:
case 1:
case 9: /* 1-Ant, Main, WLG */
default: /* 2-Ant, DPDT, WLG */
break;
case 2:
case 10: /* 1-Ant, Main, BTG */
case 7:
case 15: /* 2-Ant, DPDT, BTG */
coex_rfe->wlg_at_btg = true;
break;
case 3:
case 11: /* 1-Ant, Aux, WLG */
coex_rfe->ant_switch_polarity = 1;
break;
case 4:
case 12: /* 1-Ant, Aux, BTG */
coex_rfe->wlg_at_btg = true;
coex_rfe->ant_switch_polarity = 1;
break;
case 5:
case 13: /* 2-Ant, no switch, WLG */
case 6:
case 14: /* 2-Ant, no antenna switch, WLG */
coex_rfe->ant_switch_exist = false;
break;
}
}
static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_efuse *efuse = &rtwdev->efuse;
bool share_ant = efuse->share_ant;
if (share_ant)