diff --git a/doc/lxp32-trm.pdf b/doc/lxp32-trm.pdf
index 7565acc..237c72d 100644
Binary files a/doc/lxp32-trm.pdf and b/doc/lxp32-trm.pdf differ
diff --git a/doc/src/trm/frontmatter.tex b/doc/src/trm/frontmatter.tex
index 0d4ba30..2f6ff9f 100644
--- a/doc/src/trm/frontmatter.tex
+++ b/doc/src/trm/frontmatter.tex
@@ -15,7 +15,7 @@
 	\Large a lightweight open source 32-bit CPU core\par
 	\LARGE \textbf{Technical Reference Manual}\par
 	\vspace{1.2\onelineskip}
-	\large Version 1.3\par
+	\large Version 1.4\par
 	\vspace*{4\onelineskip}
 	\end{center}
 	\vspace*{\fill}
diff --git a/doc/src/trm/lxp32-trm.tex b/doc/src/trm/lxp32-trm.tex
index 8f06897..4ee359e 100644
--- a/doc/src/trm/lxp32-trm.tex
+++ b/doc/src/trm/lxp32-trm.tex
@@ -1857,6 +1857,10 @@ \section{Data bus}
 
 \chapter{List of changes}
 
+\section*{Version 1.4 (2024-11-02)}
+
+This release introduces support for level triggered interrupts.
+
 \section*{Version 1.3 (2022-08-28)}
 
 This release removes support for temporarily blocked interrupts (interrupts can still be disabled) and introduces wake-up interrupts.