From af97cc40a99205f9dfeccd3b87f8c5f96bd8475b Mon Sep 17 00:00:00 2001
From: lyrakisk <24938740+lyrakisk@users.noreply.github.com>
Date: Tue, 9 Apr 2024 19:21:56 +0200
Subject: [PATCH] Implement CLV instruction

---
 README.md               |  2 +-
 src/cpu/instructions.rs |  1 +
 src/cpu/mod.rs          | 19 +++++++++++++++++++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 8c4c733..8c5204c 100644
--- a/README.md
+++ b/README.md
@@ -33,7 +33,7 @@ A (soon to be) fully-featured NES emulator written in Rust.
 - [X] CLC
 - [ ] CLD
 - [ ] CLI
-- [ ] CLV
+- [X] CLV
 - [ ] CMP
 - [ ] CPX
 - [ ] CPY
diff --git a/src/cpu/instructions.rs b/src/cpu/instructions.rs
index 764a24a..982de8a 100644
--- a/src/cpu/instructions.rs
+++ b/src/cpu/instructions.rs
@@ -73,6 +73,7 @@ pub static INSTRUCTIONS: Lazy<HashMap<u8, Instruction>> = Lazy::new(|| {
         Instruction {opcode: 0x50, name: "BVC", bytes: 2, addressing_mode: AddressingMode::Relative},
         Instruction {opcode: 0x70, name: "BVS", bytes: 2, addressing_mode: AddressingMode::Relative},
         Instruction {opcode: 0x18, name: "CLC", bytes: 1, addressing_mode: AddressingMode::Implicit},
+        Instruction {opcode: 0xB8, name: "CLV", bytes: 1, addressing_mode: AddressingMode::Implicit},
         Instruction {opcode: 0xA9, name: "LDA", bytes: 2, addressing_mode: AddressingMode::Immediate},
         Instruction {opcode: 0xA5, name: "LDA", bytes: 2, addressing_mode: AddressingMode::ZeroPage},
         Instruction {opcode: 0xB5, name: "LDA", bytes: 2, addressing_mode: AddressingMode::ZeroPage_X},
diff --git a/src/cpu/mod.rs b/src/cpu/mod.rs
index eb8b2d0..64cee9d 100644
--- a/src/cpu/mod.rs
+++ b/src/cpu/mod.rs
@@ -113,6 +113,10 @@ impl CPU {
                 self.clc();
                 None
             }
+            "CLV" => {
+                self.clv();
+                None
+            }
             "BRK" => Some(0),
             "LDA" => {
                 self.lda(&instruction.addressing_mode);
@@ -408,6 +412,10 @@ impl CPU {
         self.clear_flag(STATUS_FLAG_MASK_CARRY);
     }
 
+    fn clv(&mut self) {
+        self.clear_flag(STATUS_FLAG_MASK_OVERFLOW);
+    }
+
     fn lda(&mut self, addressing_mode: &AddressingMode) {
         let operand = self.get_operand(addressing_mode);
         self.register_a = operand;
@@ -723,6 +731,17 @@ mod test_cpu {
         assert_eq!(cpu.status, expected_status)
     }
 
+    #[test_case(0b0100_0000, 0b0000_0000)]
+    #[test_case(0b0000_0000, 0b0000_0000)]
+    #[test_case(0b0100_0001, 0b0000_0001)]
+    #[test_case(0b0000_0001, 0b0000_0001)]
+    fn test_clv(status: u8, expected_status: u8) {
+        let mut cpu = CPU::new();
+        cpu.status = status;
+        cpu.clv();
+        assert_eq!(cpu.status, expected_status)
+    }
+
     #[test_case(0b0000_0001, 0x5, 0x4, 0x1, 0b0000_0001)]
     #[test_case(0b0000_0001, 0x5, 0x5, 0x0, 0b0000_0011)]
     #[test_case(0b0000_0001, 0x0, 0x1, 0xFF, 0b1000_0000)]