diff --git a/artiq/gateware/targets/digilent_genesys2.py b/artiq/gateware/targets/digilent_genesys2.py
index 7dc325d7eb..30aff2ce06 100755
--- a/artiq/gateware/targets/digilent_genesys2.py
+++ b/artiq/gateware/targets/digilent_genesys2.py
@@ -104,8 +104,11 @@ def add_rtio(self, rtio_channels):
             [self.rtio.cri, self.rtio_dma.cri],
             [self.rtio_core.cri])
         self.register_kernel_cpu_csrdevice("cri_con")
-        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
-        self.csr_devices.append("rtio_moninj")
+
+        # Only add MonInj core if there is anything to monitor
+        if any([len(c.probes) for c in rtio_channels]):
+            self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+            self.csr_devices.append("rtio_moninj")
 
         self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
         self.platform.add_false_path_constraints(