From b9ab781e7a0cee21f24dd904990b7870facd4fa3 Mon Sep 17 00:00:00 2001
From: Harry Ho <hh@m-labs.hk>
Date: Thu, 6 Feb 2020 16:10:53 +0800
Subject: [PATCH] spi: add divisor_bits; fix simulation

---
 nmigen_stdio/spiflash.py | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/nmigen_stdio/spiflash.py b/nmigen_stdio/spiflash.py
index 64c8402..251b81a 100644
--- a/nmigen_stdio/spiflash.py
+++ b/nmigen_stdio/spiflash.py
@@ -41,8 +41,7 @@ def _format_cmd(self):
                 fcmd &= ~(1 << (bit*self.spi_width))
         return fcmd
 
-    def __init__(self, *, protocol, data_width,
-                 divisor=1, pins=None):
+    def __init__(self, *, protocol, data_width=32, divisor=1, divisor_bits=None, pins=None):
         if protocol not in ["standard", "dual", "quad"]:
             raise ValueError("Invalid SPI protocol {!r}; must be one of "
                              "\"standard\", \"dual\", or \"quad\""
@@ -53,7 +52,7 @@ def __init__(self, *, protocol, data_width,
         if divisor < 1:
             raise ValueError("Invalid divisor value; must be at least 1"
                              .format(divisor))
-        self.divisor = Signal(bits_for(divisor), reset=divisor)
+        self.divisor = Signal(divisor_bits or bits_for(divisor), reset=divisor)
         self._divisor_val = divisor + 1
 
         self._pins = pins
@@ -108,12 +107,12 @@ def _add_spi_hardware_logic(self, platform, module):
                 module.submodules += FFSynchronizer(self._pins.miso.i, self.miso)
                 module.d.comb += self._pins.mosi.o.eq(self.mosi)
             elif self._protocol in ["dual", "quad"]:
-                dq_oe = Signal()
+                self.dq_oe = Signal()
                 module.submodules.dq = platform.get_tristate(self.dq, self._pins.dq, None, False)
         # If the user doesn't give pins, create dq Pins for Dual & Quad
         else:
             if self._protocol in ["dual", "quad"]:
-                dq_oe = Signal()
+                self.dq_oe = Signal()
                 if self._protocol == "dual":
                     dq_pins = Record([
                         ("dq", Pin(width=2, dir="io", xdr=0).layout)
@@ -126,7 +125,7 @@ def _add_spi_hardware_logic(self, platform, module):
                 tristate_submodule.submodules += Instance("$tribuf",
                     p_WIDTH=self.dq.width,
                     i_EN=self.dq.oe,
-                    i_A=Platformodule._invert_if(False, self.dq.o),
+                    i_A=self.dq.o,
                     o_Y=dq_pins
                 )
                 module.submodules.dq = tristate_submodule
@@ -168,7 +167,7 @@ def _add_spi_hardware_logic(self, platform, module):
         elif self._protocol in ["dual", "quad"]:
             module.d.comb += [
                 self.dq.o.eq(shreg[-self.spi_width:]),
-                self.dq.oe.eq(dq_oe)
+                self.dq.oe.eq(self.dq_oe)
             ]
 
 
@@ -228,7 +227,7 @@ def elaborate(self, platform):
                         shreg[-self.cmd_width:].eq(fcmd)
                     ]
                     if self._protocol in ["dual", "quad"]:
-                        m.d.sync += dq_oe.eq(1)
+                        m.d.sync += self.dq_oe.eq(1)
                     m.next = "SLOWREAD-CMD"
             # State: Command, MOSI
             with m.State("SLOWREAD-CMD"):
@@ -245,7 +244,7 @@ def elaborate(self, platform):
                 with m.If(state_counter == state_durations["SLOWREAD-ADDR"] - 1):
                     m.d.sync += state_counter.eq(0)
                     if self._protocol in ["dual", "quad"]:
-                        m.d.sync += dq_oe.eq(0)
+                        m.d.sync += self.dq_oe.eq(0)
                     m.next = "SLOWREAD-READ"
                 with m.Else():
                     m.d.sync += state_counter.eq(state_counter + 1)
@@ -257,7 +256,7 @@ def elaborate(self, platform):
                         self.r_rdy.eq(1)
                     ]
                     if self._protocol in ["dual", "quad"]:
-                        m.d.sync += dq_oe.eq(0)
+                        m.d.sync += self.dq_oe.eq(0)
                     m.next = "SLOWREAD-RDYWAIT"
                 with m.Else():
                     m.d.sync += state_counter.eq(state_counter + 1)
@@ -339,7 +338,7 @@ def elaborate(self, platform):
                         shreg[-self.cmd_width:].eq(fcmd)
                     ]
                     if self._protocol in ["dual", "quad"]:
-                        m.d.sync += dq_oe.eq(1)
+                        m.d.sync += self.dq_oe.eq(1)
                     m.next = "FASTREAD-CMD"
             # State: Command, MOSI
             with m.State("FASTREAD-CMD"):
@@ -356,7 +355,7 @@ def elaborate(self, platform):
                 with m.If(state_counter == state_durations["FASTREAD-ADDR"] - 1):
                     m.d.sync += state_counter.eq(0)
                     if self._protocol in ["dual", "quad"]:
-                        m.d.sync += dq_oe.eq(0)
+                        m.d.sync += self.dq_oe.eq(0)
                     m.next = "FASTREAD-WAITREAD"
                 with m.Else():
                     m.d.sync += state_counter.eq(state_counter + 1)
@@ -368,7 +367,7 @@ def elaborate(self, platform):
                         self.r_rdy.eq(1)
                     ]
                     if self._protocol in ["dual", "quad"]:
-                        m.d.sync += dq_oe.eq(0)
+                        m.d.sync += self.dq_oe.eq(0)
                     m.next = "FASTREAD-RDYWAIT"
                 with m.Else():
                     m.d.sync += state_counter.eq(state_counter + 1)