cpu_wavedata_group17.vcd

$date
	Tue Jul 04 10:49:46 2023
$end
$version
	Icarus Verilog
$end
$timescale
	100ps
$end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 ! \register[0] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 " \register[1] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 # \register[2] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 $ \register[3] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 % \register[4] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 & \register[5] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 ' \register[6] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$scope module mycpu $end
$scope module group17RegisterFile $end
$var reg 8 ( \register[7] [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module cpu_tb $end
$var wire 1 ) BUSYWAIT $end
$var wire 8 * WRITEDATA [7:0] $end
$var wire 1 + WRITE $end
$var wire 1 , READ $end
$var wire 32 - PC [31:0] $end
$var wire 32 . MEM_WRITEDATA [31:0] $end
$var wire 1 / MEM_WRITE $end
$var wire 32 0 MEM_READDATA [31:0] $end
$var wire 1 1 MEM_READ $end
$var wire 1 2 MEM_BUSYWAIT $end
$var wire 6 3 MEM_ADDRESS [5:0] $end
$var wire 128 4 INST_MEM_READDATA [127:0] $end
$var wire 1 5 INST_MEM_READ $end
$var wire 1 6 INST_MEM_BUSYWAIT $end
$var wire 6 7 INST_MEM_ADDRESS [5:0] $end
$var wire 1 8 INST_BUSYWAIT $end
$var wire 32 9 INSTRUCTION [31:0] $end
$var wire 1 : DATA_BUSYWAIT $end
$var wire 8 ; CACHE_READDATA [7:0] $end
$var wire 8 < ADDRESS [7:0] $end
$var reg 1 = CLK $end
$var reg 1 > RESET $end
$scope module group17_data_cache $end
$var wire 1 = clock $end
$var wire 1 ? dirty $end
$var wire 1 @ hitsignal $end
$var wire 1 > reset $end
$var wire 3 A tag [2:0] $end
$var wire 1 B valid $end
$var wire 8 C writedata [7:0] $end
$var wire 1 + write $end
$var wire 8 D readdata [7:0] $end
$var wire 1 , read $end
$var wire 32 E mem_readdata [31:0] $end
$var wire 1 2 mem_busywait $end
$var wire 1 F comparatorsignal $end
$var wire 8 G address [7:0] $end
$var parameter 3 H CACHE_UPDATE $end
$var parameter 3 I IDLE $end
$var parameter 3 J MEM_READ $end
$var parameter 3 K MEM_WRITE $end
$var reg 1 : busywait $end
$var reg 32 L data [31:0] $end
$var reg 6 M mem_address [5:0] $end
$var reg 1 1 mem_read $end
$var reg 1 / mem_write $end
$var reg 32 N mem_writedata [31:0] $end
$var reg 3 O next_state [2:0] $end
$var reg 3 P state [2:0] $end
$var integer 32 Q i [31:0] $end
$upscope $end
$scope module group17_data_memory $end
$var wire 6 R address [5:0] $end
$var wire 1 = clock $end
$var wire 1 1 read $end
$var wire 1 > reset $end
$var wire 1 / write $end
$var wire 32 S writedata [31:0] $end
$var reg 1 2 busywait $end
$var reg 1 T readaccess $end
$var reg 32 U readdata [31:0] $end
$var reg 1 V writeaccess $end
$var integer 32 W i [31:0] $end
$upscope $end
$scope module group17_instruction_cache $end
$var wire 1 = clock $end
$var wire 1 X hitsignal $end
$var wire 1 > reset $end
$var wire 3 Y tag [2:0] $end
$var wire 1 Z valid $end
$var wire 32 [ instruction [31:0] $end
$var wire 128 \ inst_readdata [127:0] $end
$var wire 1 6 inst_busywait $end
$var wire 1 ] comparatorsignal $end
$var wire 32 ^ PC [31:0] $end
$var parameter 2 _ CACHE_UPDATE $end
$var parameter 2 ` IDLE $end
$var parameter 2 a MEM_READ $end
$var reg 10 b address [9:0] $end
$var reg 1 8 busywait $end
$var reg 128 c data [127:0] $end
$var reg 6 d inst_address [5:0] $end
$var reg 1 5 inst_read $end
$var reg 2 e next_state [1:0] $end
$var reg 2 f state [1:0] $end
$var integer 32 g i [31:0] $end
$upscope $end
$scope module group17_instruction_memory $end
$var wire 6 h address [5:0] $end
$var wire 1 = clock $end
$var wire 1 5 read $end
$var reg 1 6 busywait $end
$var reg 1 i readaccess $end
$var reg 128 j readinst [127:0] $end
$upscope $end
$scope module mycpu $end
$var wire 8 k ADDRESS [7:0] $end
$var wire 1 ) BUSYWAIT $end
$var wire 1 = CLK $end
$var wire 32 l INSTRUCTION [31:0] $end
$var wire 1 m IS_BEQ $end
$var wire 1 n IS_J_OR_BEQ $end
$var wire 8 o READDATA [7:0] $end
$var wire 1 > RESET $end
$var wire 8 p WRITEDATA [7:0] $end
$var wire 1 q WRITEINREG $end
$var wire 1 r ZERO $end
$var wire 3 s WRITEREG [2:0] $end
$var wire 1 t WRITEENABLE $end
$var wire 1 + WRITE $end
$var wire 8 u REGOUT2 [7:0] $end
$var wire 8 v REGOUT1 [7:0] $end
$var wire 3 w READREG2 [2:0] $end
$var wire 3 x READREG1 [2:0] $end
$var wire 1 , READ $end
$var wire 32 y PCOUT_JBeq [31:0] $end
$var wire 32 z PCOUT_EXECUTING [31:0] $end
$var wire 32 { PCOUT [31:0] $end
$var wire 32 | PC [31:0] $end
$var wire 8 } OPCODE [7:0] $end
$var wire 8 ~ OFFSET_8BIT [7:0] $end
$var wire 32 !" OFFSET_32BIT_SHIFTED [31:0] $end
$var wire 32 "" OFFSET_32BIT [31:0] $end
$var wire 1 #" MUXIMMSELECT $end
$var wire 8 $" MUXIMMOUT [7:0] $end
$var wire 1 %" MUXDATAMEMSELECT $end
$var wire 8 &" MUXDATAMEMOUT [7:0] $end
$var wire 1 '" MUXCOMPSELECT $end
$var wire 8 (" MUXCOMPOUT [7:0] $end
$var wire 1 )" J_TRIGGER $end
$var wire 8 *" IMMEDIATE [7:0] $end
$var wire 8 +" COMPLIMENT [7:0] $end
$var wire 1 ," BEQ_TRIGGER $end
$var wire 8 -" ALURESULT [7:0] $end
$var wire 3 ." ALUOP [2:0] $end
$scope module group17ALU $end
$var wire 3 /" SELECT [2:0] $end
$var wire 8 0" RESULT_FOR_OR [7:0] $end
$var wire 8 1" RESULT_FOR_FORWARD [7:0] $end
$var wire 8 2" RESULT_FOR_AND [7:0] $end
$var wire 8 3" RESULT_FOR_ADD [7:0] $end
$var wire 8 4" DATA2 [7:0] $end
$var wire 8 5" DATA1 [7:0] $end
$var reg 8 6" RESULT [7:0] $end
$var reg 1 r ZERO $end
$scope module add_1 $end
$var wire 8 7" RESULT [7:0] $end
$var wire 8 8" DATA2 [7:0] $end
$var wire 8 9" DATA1 [7:0] $end
$upscope $end
$scope module and_1 $end
$var wire 8 :" RESULT [7:0] $end
$var wire 8 ;" DATA2 [7:0] $end
$var wire 8 <" DATA1 [7:0] $end
$upscope $end
$scope module forward_1 $end
$var wire 8 =" RESULT [7:0] $end
$var wire 8 >" DATA2 [7:0] $end
$upscope $end
$scope module or_1 $end
$var wire 8 ?" RESULT [7:0] $end
$var wire 8 @" DATA2 [7:0] $end
$var wire 8 A" DATA1 [7:0] $end
$upscope $end
$upscope $end
$scope module group17ControlUnit $end
$var wire 1 ) BUSYWAIT $end
$var wire 8 B" OPCODE [7:0] $end
$var reg 3 C" ALUOP [2:0] $end
$var reg 1 ," BEQ_TRIGGER $end
$var reg 1 )" J_TRIGGER $end
$var reg 1 '" MUXCOMP $end
$var reg 1 %" MUXDATAMEM $end
$var reg 1 #" MUXIMM $end
$var reg 1 , READ $end
$var reg 1 + WRITE $end
$var reg 1 t WRITEENABLE $end
$upscope $end
$scope module group17Decorder $end
$var wire 32 D" INSTRUCTION [31:0] $end
$var reg 8 E" IMMEDIATE [7:0] $end
$var reg 8 F" OFFSET_8BIT [7:0] $end
$var reg 8 G" OPCODE [7:0] $end
$var reg 3 H" READREG1 [2:0] $end
$var reg 3 I" READREG2 [2:0] $end
$var reg 3 J" WRITEREG [2:0] $end
$upscope $end
$scope module group17MUXCompliment $end
$var wire 1 '" SELECT $end
$var wire 8 K" IN2 [7:0] $end
$var wire 8 L" IN1 [7:0] $end
$var reg 8 M" OUT [7:0] $end
$upscope $end
$scope module group17MUXImmediate $end
$var wire 8 N" IN1 [7:0] $end
$var wire 8 O" IN2 [7:0] $end
$var wire 1 #" SELECT $end
$var reg 8 P" OUT [7:0] $end
$upscope $end
$scope module group17MUXRegWriteData $end
$var wire 8 Q" IN1 [7:0] $end
$var wire 8 R" IN2 [7:0] $end
$var wire 1 %" SELECT $end
$var reg 8 S" OUT [7:0] $end
$upscope $end
$scope module group17Mux2to1_32bit $end
$var wire 1 n SELECT $end
$var wire 32 T" IN2 [31:0] $end
$var wire 32 U" IN1 [31:0] $end
$var reg 32 V" OUT [31:0] $end
$upscope $end
$scope module group17PCAdder $end
$var wire 32 W" PC [31:0] $end
$var reg 32 X" PCOUT [31:0] $end
$upscope $end
$scope module group17PCAdderJBeq $end
$var wire 32 Y" INSTRUCTION [31:0] $end
$var wire 32 Z" PC [31:0] $end
$var wire 32 [" OFFSET [31:0] $end
$var reg 32 \" PCOUT_JBeq [31:0] $end
$upscope $end
$scope module group17ProgramCounter $end
$var wire 1 ) BUSYWAIT $end
$var wire 1 = CLK $end
$var wire 32 ]" PCOUT_EXECUTING [31:0] $end
$var wire 1 > RESET $end
$var reg 32 ^" PC [31:0] $end
$upscope $end
$scope module group17RegisterFile $end
$var wire 1 = CLK $end
$var wire 8 _" IN [7:0] $end
$var wire 3 `" INADDRESS [2:0] $end
$var wire 8 a" OUT1 [7:0] $end
$var wire 3 b" OUT1ADDRESS [2:0] $end
$var wire 8 c" OUT2 [7:0] $end
$var wire 3 d" OUT2ADDRESS [2:0] $end
$var wire 1 > RESET $end
$var wire 1 q WRITE $end
$var integer 32 e" i [31:0] $end
$upscope $end
$scope module group17Shifter $end
$var wire 32 f" OFFSET [31:0] $end
$var reg 32 g" OFFSET_SHIFTED [31:0] $end
$upscope $end
$scope module group17SignExtend $end
$var wire 8 h" OFFSET_8BIT [7:0] $end
$var reg 32 i" OFFSET_32BIT [31:0] $end
$upscope $end
$scope module group17TwosCompliment $end
$var wire 8 j" IN [7:0] $end
$var reg 8 k" COMPLIMENT [7:0] $end
$var reg 8 l" TEMP [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b1 a
b0 `
b10 _
b10 K
b1 J
b0 I
b11 H
$end
#0
$dumpvars
bx l"
bx k"
bx j"
bx i"
bx h"
bx g"
bx f"
b1000 e"
bx d"
bx c"
bx b"
bx a"
bx `"
bx _"
bx ^"
bx ]"
bx \"
bx ["
bx Z"
bx Y"
bx X"
bx W"
bx V"
bx U"
bx T"
bx S"
bx R"
bx Q"
bx P"
bx O"
bx N"
bx M"
bx L"
bx K"
bx J"
bx I"
bx H"
bx G"
bx F"
bx E"
bx D"
bx C"
bx B"
bx A"
bx @"
bx ?"
bx >"
bx ="
bx <"
bx ;"
bx :"
bx 9"
bx 8"
bx 7"
bx 6"
bx 5"
bx 4"
bx 3"
bx 2"
bx 1"
bx 0"
bx /"
bx ."
bx -"
x,"
bx +"
bx *"
x)"
bx ("
x'"
bx &"
x%"
bx $"
x#"
bx ""
bx !"
bx ~
bx }
bx |
bx {
bx z
bx y
bx x
bx w
bx v
bx u
xt
bx s
xr
xq
bx p
bx o
xn
xm
bx l
bx k
bx j
0i
bx h
b1000 g
b0 f
b0 e
bx d
bx c
bx b
bx ^
x]
bx \
bx [
xZ
bx Y
xX
b100000000 W
0V
bx U
0T
bx S
bx R
b1000 Q
b0 P
b0 O
bx N
bx M
bx L
bx G
xF
bx E
bx D
bx C
xB
bx A
x@
x?
1>
0=
bx <
bx ;
0:
bx 9
08
bx 7
06
05
bx 4
bx 3
02
01
bx 0
0/
bx .
bx -
0,
0+
bx *
0)
bx (
bx '
bx &
bx %
bx $
bx #
bx "
bx !
$end
#40
1=
#50
b0 (
b0 '
b0 &
b0 %
b0 $
b0 #
b0 "
b0 !
0q
1)
18
b0 b
b0 -
b0 ^
b0 |
b0 W"
b0 ^"
b1000 e"
#60
b1 e
0X
b100 z
b100 V"
b100 ]"
b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx c
0Z
b100 {
b100 U"
b100 X"
b100 Z"
#80
0=
#100
1i
16
b0 7
b0 d
b0 h
15
b1 e
b1 f
b1000 Q
b1000 g
0>
#120
1=
#160
0=
#200
1=
#240
0=
#280
1=
#320
0=
#360
1=
#400
0=
#440
1=
#480
0=
#520
1=
bx00011001 4
bx00011001 \
bx00011001 j
#560
0=
#600
1=
#640
0=
#680
1=
#720
0=
#760
1=
#800
0=
#840
1=
#880
0=
#920
1=
bx0000000000011001 4
bx0000000000011001 \
bx0000000000011001 j
#960
0=
#1000
1=
#1040
0=
#1080
1=
#1120
0=
#1160
1=
#1200
0=
#1240
1=
#1280
0=
#1320
1=
bx000001000000000000011001 4
bx000001000000000000011001 \
bx000001000000000000011001 j
#1360
0=
#1400
1=
#1440
0=
#1480
1=
#1520
0=
#1560
1=
#1600
0=
#1640
1=
#1680
0=
#1720
1=
bx00000000000001000000000000011001 4
bx00000000000001000000000000011001 \
bx00000000000001000000000000011001 j
#1760
0=
#1800
1=
#1840
0=
#1880
1=
#1920
0=
#1960
1=
#2000
0=
#2040
1=
#2080
0=
#2120
1=
bx0010001100000000000001000000000000011001 4
bx0010001100000000000001000000000000011001 \
bx0010001100000000000001000000000000011001 j
#2160
0=
#2200
1=
#2240
0=
#2280
1=
#2320
0=
#2360
1=
#2400
0=
#2440
1=
#2480
0=
#2520
1=
bx000000000010001100000000000001000000000000011001 4
bx000000000010001100000000000001000000000000011001 \
bx000000000010001100000000000001000000000000011001 j
#2560
0=
#2600
1=
#2640
0=
#2680
1=
#2720
0=
#2760
1=
#2800
0=
#2840
1=
#2880
0=
#2920
1=
bx00000101000000000010001100000000000001000000000000011001 4
bx00000101000000000010001100000000000001000000000000011001 \
bx00000101000000000010001100000000000001000000000000011001 j
#2960
0=
#3000
1=
#3040
0=
#3080
1=
#3120
0=
#3160
1=
#3200
0=
#3240
1=
#3280
0=
#3320
1=
bx0000000000000101000000000010001100000000000001000000000000011001 4
bx0000000000000101000000000010001100000000000001000000000000011001 \
bx0000000000000101000000000010001100000000000001000000000000011001 j
#3360
0=
#3400
1=
#3440
0=
#3480
1=
#3520
0=
#3560
1=
#3600
0=
#3640
1=
#3680
0=
#3720
1=
bx000001010000000000000101000000000010001100000000000001000000000000011001 4
bx000001010000000000000101000000000010001100000000000001000000000000011001 \
bx000001010000000000000101000000000010001100000000000001000000000000011001 j
#3760
0=
#3800
1=
#3840
0=
#3880
1=
#3920
0=
#3960
1=
#4000
0=
#4040
1=
#4080
0=
#4120
1=
bx00000100000001010000000000000101000000000010001100000000000001000000000000011001 4
bx00000100000001010000000000000101000000000010001100000000000001000000000000011001 \
bx00000100000001010000000000000101000000000010001100000000000001000000000000011001 j
#4160
0=
#4200
1=
#4240
0=
#4280
1=
#4320
0=
#4360
1=
#4400
0=
#4440
1=
#4480
0=
#4520
1=
bx0000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 4
bx0000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 \
bx0000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 j
#4560
0=
#4600
1=
#4640
0=
#4680
1=
#4720
0=
#4760
1=
#4800
0=
#4840
1=
#4880
0=
#4920
1=
bx000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 4
bx000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 \
bx000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 j
#4960
0=
#5000
1=
#5040
0=
#5080
1=
#5120
0=
#5160
1=
#5200
0=
#5240
1=
#5280
0=
#5320
1=
bx01011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 4
bx01011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 \
bx01011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 j
#5360
0=
#5400
1=
#5440
0=
#5480
1=
#5520
0=
#5560
1=
#5600
0=
#5640
1=
#5680
0=
#5720
1=
bx0000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 4
bx0000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 \
bx0000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 j
#5760
0=
#5800
1=
#5840
0=
#5880
1=
#5920
0=
#5960
1=
#6000
0=
#6040
1=
#6080
0=
#6120
1=
bx000000010000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 4
bx000000010000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 \
bx000000010000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 j
#6160
0=
#6200
1=
#6240
0=
#6280
1=
#6320
0=
#6360
1=
#6400
0=
#6440
1=
#6480
0=
#6520
bx 7
bx d
bx h
05
b10 f
b0 e
1=
0i
06
b10000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 4
b10000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 \
b10000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 j
#6540
xX
b10000000001011010000000100000011000000100000001010000000000000101000000000010001100000000000001000000000000011001 c
1Z
b0 Y
#6549
1X
1]
#6550
b100 s
b100 J"
b100 `"
b0 x
b0 H"
b0 b"
b1 w
b1 I"
b1 d"
b11001 *"
b11001 E"
b11001 O"
b0 }
b0 B"
b0 G"
b1000000000000011001 9
b1000000000000011001 [
b1000000000000011001 l
b1000000000000011001 D"
b1000000000000011001 Y"
#6560
0n
0m
b11001 $"
b11001 4"
b11001 8"
b11001 ;"
b11001 >"
b11001 @"
b11001 P"
0%"
0,"
0)"
1t
1#"
0'"
b0 ."
b0 /"
b0 C"
0=
#6570
b11001 &"
b11001 S"
b11001 _"
b0 ("
b0 M"
b0 N"
b0 l"
bx11xx1 0"
bx11xx1 ?"
b0xx00x 2"
b0xx00x :"
b11001 <
b11001 G
b11001 k
b11001 -"
b11001 6"
b11001 Q"
b11001 1"
b11001 ="
b0 *
b0 C
b0 p
b0 v
b0 5"
b0 9"
b0 <"
b0 A"
b0 a"
b0 u
b0 L"
b0 c"
b0 j"
#6580
0@
0?
0B
b11001 0"
b11001 ?"
b0 2"
b0 :"
b0 +"
b0 K"
b0 k"
#6590
0r
b11001 3"
b11001 7"
#6600
1q
0)
b0 f
08
1=
#6640
0=
#6680
1=
#6690
b11001 %
0q
1)
18
b100 b
b100 -
b100 ^
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1=
bx000000100000000100000101000001100000001100000001xxxxxxxxxxxxxxxx 4
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