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hp2100_cpu5.c
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/* hp2100_cpu5.c: HP 1000 EMA, VIS, and SIGNAL microcode simulator
Copyright (c) 2007-2008, Holger Veit
Copyright (c) 2006-2019, J. David Bryan
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of the authors shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the authors.
CPU5 Extended Memory Array, Vector Instruction Set, and SIGNAL/1000
instructions
23-Jan-19 JDB Moved fmt_ab from hp2100_cpu1.c
02-Aug-18 JDB Moved VMA dispatcher to hp2100_cpu7.c
Moved VIS dispatcher from hp2100_cpu7.c
30-Jul-18 JDB Renamed "dms_[rw]map" to "meu_read_map", "meu_write_map"
07-Sep-17 JDB Replaced "uint16" casts with "HP_WORD" for A/B assignments
15-Jul-17 JDB Replaced "vma_resolve" with "resolve"
26-Jun-17 JDB Replaced SEXT with SEXT16
06-Jun-17 HV Fixed bug in cpu_vma_lbp "last suit + 1" handler
31-Jan-17 JDB Revised to use tprintf and TRACE_OPND for debugging
26-Jan-17 JDB Removed debug parameters from ema_* routines
24-Jan-17 JDB Replaced ReadIO, WriteIO with ReadS/U, WriteS/U
05-Aug-16 JDB Renamed the P register from "PC" to "PR"
24-Dec-14 JDB Added casts for explicit downward conversions
17-Dec-12 JDB Fixed cpu_vma_mapte to return FALSE if not a VMA program
09-May-12 JDB Separated assignments from conditional expressions
23-Mar-12 JDB Added sign extension for dim count in "ema_resolve"
28-Dec-11 JDB Eliminated unused variable in "vis_vset"
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
30-Jul-08 JDB Redefined ABORT to pass address, moved def to hp2100_cpu.h
26-Jun-08 JDB Rewrote device I/O to model backplane signals
01-May-08 HV Fixed mapping bug in "ema_emap"
21-Apr-08 JDB Added EMA support from Holger
25-Nov-07 JDB Added TF fix from Holger
07-Nov-07 HV VMACK diagnostic tests 1...32 passed
19-Oct-07 JDB Corrected $LOC operand profile to OP_CCCACC
03-Oct-07 HV Moved RTE-6/VM instrs from hp2100_cpu0.c
26-Sep-06 JDB Created
Primary references:
- HP 1000 M/E/F-Series Computers Technical Reference Handbook
(5955-0282, March 1980)
- HP 1000 M/E/F-Series Computers Engineering and Reference Documentation
(92851-90001, March 1981)
- Macro/1000 Reference Manual
(92059-90001, December 1992)
The RTE-IV and RTE-IVB Extended Memory Array instructions and the RTE-6/VM
Virtual Memory Area instructions were added to accelerate the logical-to-
physical address translations and array subscript calculations of programs
running under the RTE-IV (HP product number 92067A), RTE-IVB (92068A), and
RTE-6/VM (92084A) operating systems. Microcode was available for the E- and
F-Series; the M-Series used software equivalents.
Both EMA and VMA opcodes reside in the range 105240-105257, so only one or
the other could be installed in a given system. This did not present a
difficulty, as VMA was a superset of EMA. The EMA encodings are:
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 0 0 | .EMIO
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| buffer size address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| array table address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| last subscript address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: ... :
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| first subscript address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: return location if error : P+n
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if buffer is mapped : P+n+1
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
The .EMIO instruction maps a buffer of the indicated size and starting at the
indicated array location into memory. It ensures that the buffer is entirely
within the logical address space in preparation for an I/O operation.
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 0 1 | MMAP
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| relative page count from EMA start to segment start address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| page count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The MMAP instruction maps a sequence of physical memory pages into the
mapping segment area of a program's logical address space. The A-register
value on return indicates the success or failure of the request.
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 1 0 | emtst
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The emtst instruction is used to determine if the EMA firmware has been
installed. If it is executed in single-step mode, it sets S to 102077 (HLT
77B). It executes as NOP from a running program.
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 1 1 1 | .EMAP
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| array address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| array table address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| last subscript address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: ... :
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| first subscript address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: return location if error : P+n
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if page is mapped : P+n+1
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
The .EMAP instruction resolves an array access into the memory address of the
referenced element. If the array is in EMA, it also maps the element into
the mapping segment.
The Vector Instruction Set (VIS) provides instructions that operate on
one-dimensional arrays of floating-point values. Both single- and
double-precision operations are supported. VIS uses the F-Series
floating-point processor to handle the floating-point math, so the firmware
is supported only on that machine.
Instructions use IR bit 11 to select single- or double-precision format. The
double-precision instruction names begin with "D" (e.g., DVADD vs. VADD).
Most VIS instructions are two words in length, with a sub-opcode immediately
following the primary opcode.
The two-word instructions are interruptible. the firmware sets bit 15 of the
second word to 1 to indicate that the instruction has been interrupted. This
allows the instruction to resume at the correct point in the vector
operation. Bit 15 is set to 0 before exiting for instruction completion.
The .ESEG instruction behaves slightly differently when invoked with the
105475 opcode. The microcode source calls it a .VPRG instruction, but the
only difference is that it sets the MSEG start and size to 0 and 32,
respectively, instead of obtaining them from the ID extension. In all other
respects, the instructions are identical.
The .ERES, .VSET, and test instructions do not test bit 11, so they will be
invoked with either the 101xxx or 105xxx forms. The 101xxx forms are
canonical for the first two, while the 105xxx form is canonical for the
self-test instruction.
The VIS encodings are:
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VADD
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 0 0 0 | 0 0 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSUB
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 0 0 0 | 0 1 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VMPY
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 0 0 0 | 1 0 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VDIV
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 0 0 0 | 1 1 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSAD
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 1 0 0 | 0 0 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSSB
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 1 0 0 | 0 1 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSMY
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 1 0 0 | 1 0 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSDV
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 0 0 | P | 0 0 | 1 0 0 | 1 1 0 | 0 | P | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 1 | (D)VPIV
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 3 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 1 0 | (D)VABS
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 1 1 | (D)VSUM
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 0 0 | (D)VNRM
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 0 1 | (D)VDOT
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 1 0 | (D)VMAX
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 1 1 | (D)VMAB
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 0 0 | (D)VMIN
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 0 1 | (D)VMIB
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 1 0 | (D)VMOV
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 1 1 | (D)VSWP
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | - - - - - - - - - - - - - - - |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| increment 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| element count address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 0 0 1 | 1 0 0 | 1 1 1 | 1 0 0 | .ERES
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| array address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| array table address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| last subscript address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: ... :
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| first subscript address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: return location if error : P+n
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if page is mapped : P+n+1
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 0 0 1 | 1 0 0 | 1 1 1 | 1 0 1 | .ESEG
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| array table address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: return location if error : P+3
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if page is mapped : P+4
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 0 0 1 | 1 0 0 | 1 1 1 | 1 1 0 | .VSET
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| input vector address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| output vector address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| map table address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| scalar count |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector count |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| elements per page count |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: return location if error : P+8
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if setup is hard : P+9
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if setup is easy : P+10
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 1 | 1 1 1 | test
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: return location if the firmware is not installed : P+1
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if the firmware is installed : P+2
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
The test instruction is used to determine if the VIS firmware has been
installed. It sets X to the firmware revision code, S to 102077 (HLT 77B)
and skips the next instruction if the microcode is present.
The SIGNAL/1000 instructions provide fast Fourier transforms and complex
arithmetic. They utilize the F-Series floating-point processor and the
Vector Instruction Set, so the firmware is supported only on the F-Series
CPU.
The SIGNAL encodings are:
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 0 0 | BITRV
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| array base address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| index bitmap address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| count of index bits address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 0 1 | BTRFY
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| complex vector address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| real part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| imaginary part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| node address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| maximum length address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 1 0 | UNSCR
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| real part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| imaginary part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| index 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| index 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 1 1 | PRSCR
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| vector address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| real part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| imaginary part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| index 1 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| index 2 address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 0 0 | BITR1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| real array base address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| imaginary array base address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| index bitmap address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| count of index bits address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 0 1 | BTRF1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| real vector part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| imaginary vector part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| real part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| imaginary part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| node address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| maximum length address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 1 0 | .CADD
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| augend address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| addend address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 1 1 | .CSUB
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| minuend address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| subtrahend address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 0 0 | .CMPY
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| multiplicand address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| multiplier address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 0 1 | .CDIV
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| dividend address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| divisor address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 1 0 | CONJG
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| argument address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 1 1 | ..CCM
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| argument address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 1 0 0 | AIMAG
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| operand address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 1 0 1 | CMPLX
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| return address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| result address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| real part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| imaginary part address |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 1 1 1 | test
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
: return location if the firmware is not installed : P+1
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
: return location if the firmware is installed : P+2
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
The test instruction is used to determine if the SIGNAL firmware has been
installed. It sets X to the firmware revision code, S to 102077 (HLT 77B)
and skips the next instruction if the microcode is present.
Implementation notes:
1. As the VIS and SIGNAL firmware uses the F-Series Floating-Point
Processor, and the FPP simulator requires 64-bit integer support, VIS and
SIGNAL also require 64-bit support.
*/
#include "hp2100_defs.h"
#include "hp2100_cpu.h"
#include "hp2100_cpu_dmm.h"
#include "hp2100_cpu_fp.h"
/* Paging constants */
#define MSEG_MASK 0076000u
/* RTE base page addresses */
static const HP_WORD idx = 0001645u;
static const HP_WORD xeqt = 0001717u;
static const HP_WORD umaps = 0003740u;
/* VIS operand accessors */
#define GET_MSIGN(op) ((op)->fpk [0] & D16_SIGN)
/* SIGNAL operand address accessors */
#define RE(x) (x + 0)
#define IM(x) (x + 2)
/* EMA utility structure declarations */
typedef struct ema4 {
uint32 mseg; /* logical start of MSEG */
uint32 msegsz; /* size of std mseg in pgs */
uint32 pgoff; /* pg # in EMA containing element */
uint32 offs; /* offset into page of element */
uint32 msoff; /* total offset to element in MSEG */
uint32 emasz; /* size of ema in pgs */
uint32 msegno; /* # of std mseg */
uint32 ipgs; /* # of pgs to start of MSEG */
uint32 npgs; /* # of pgs needed */
uint32 spmseg; /* first phys pg of MSEG */
} EMA4;
/* EMA local utility routine declarations */
static t_stat ema_emap (uint32* rtn, uint32 abase, uint32 dtbl, uint32 atbl);
static t_stat ema_emio (uint32* rtn, uint32 bufl, uint32 dtbl, uint32 atbl);
static t_stat ema_mmap (uint32 ipage, uint32 npgs);
static t_bool ema_resolve (uint32 dtbl, uint32 atbl, uint32* sum);
static t_bool ema_emas (uint32 dtbl, uint32 atbl, EMA4* e);
static t_bool ema_emat (EMA4* e);
static t_bool ema_mmap01 (EMA4* e);
static t_bool ema_mmap02 (EMA4* e);
static const char *fmt_ab (t_bool success);
#if defined (HAVE_INT64) /* int64 support available */
/* VIS local utility routine declarations */
static void vis_svop (uint32 subcode, OPS op, OPSIZE opsize);
static void vis_vvop (uint32 subcode, OPS op, OPSIZE opsize);
static void vis_abs (OP* in, OPSIZE opsize);
static void vis_minmax (OPS op, OPSIZE opsize, t_bool domax, t_bool doabs);
static void vis_vpiv (OPS op, OPSIZE opsize);
static void vis_vabs (OPS op, OPSIZE opsize);
static void vis_trunc (OP* out, OP in);
static void vis_vsmnm (OPS op, OPSIZE opsize, t_bool doabs);
static void vis_vdot (OPS op, OPSIZE opsize);
static void vis_movswp (OPS op, OPSIZE opsize, t_bool doswp);
static t_stat vis_eres (HP_WORD *rtn, uint32 dtbl, uint32 atbl);
static t_stat vis_eseg (HP_WORD *rtn, uint32 tbl);
static t_stat vis_vset (HP_WORD *rtn, OPS op);
/* SIGNAL local utility routine declarations */
static void sig_caddsub (uint16 addsub, OPS op);
static void sig_btrfy (uint32 re, uint32 im, OP wr, OP wi, uint32 k, uint32 n2);
static void sig_bitrev (uint32 re, uint32 im, uint32 idx, uint32 log2n, int sz);
static OP sig_scadd (uint16 oper, t_bool addh, OP a, OP b);
static void sig_cmul (OP *r, OP *i, OP a, OP b, OP c, OP d);
#endif /* int64 conditional */
/* Global instruction executors */
/* RTE-IV Extended Memory Array instructions.
The RTE-IV operating system (HP product number 92067A) introduced the
Extended Memory Area (EMA) instructions. EMA provided a mappable data area
up to one megaword in size. These three instructions accelerated data
accesses to variables stored in EMA partitions. Support was limited to
E/F-Series machines; M-Series machines used software equivalents.
Option implementation by CPU was as follows:
2114 2115 2116 2100 1000-M 1000-E 1000-F
------ ------ ------ ------ ------ ------ ------
N/A N/A N/A N/A N/A 92067A 92067A
The routines are mapped to instruction codes as follows:
Instr. 1000-E/F Description
------ -------- ----------------------------------------------
.EMIO 105240 EMA I/O
MMAP 105241 Map physical to logical memory
emtst 105242 [self test]
.EMAP 105257 Resolve array element address
Additional references:
- RTE-IVB Programmer's Reference Manual (92068-90004, December 1983).
- RTE-IVB Technical Specifications (92068-90013, January 1980).
Implemenation notes:
1. RTE-IV EMA and RTE-6 VMA instructions share the same address space, so a
given machine can run one or the other, but not both.
2. The EMA diagnostic (92067-16013) reports bogus MMAP failures if it is
not loaded at the start of its partition (e.g., because of a LOADR "LO"
command). The "ICMPS" map comparison check in the diagnostic assumes
that the starting page of the program's partition contains the first
instruction of the program and prints "MMAP ERROR" if it does not.
*/
static const OP_PAT op_ema[16] = {
OP_AKA, OP_AKK, OP_N, OP_N, /* .EMIO MMAP [test] --- */
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
OP_N, OP_N, OP_N, OP_N, /* --- --- --- --- */
OP_N, OP_N, OP_N, OP_AAA /* --- --- --- .EMAP */
};
t_stat cpu_rte_ema (void)
{
t_stat reason = SCPE_OK;
OPS op;
OP_PAT pattern;
uint32 entry, rtn;