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| Design | M/S | L/S | M/F | L/F | Extra | Total | Place |
|---|---|---|---|---|---|---|---|
| spinalHDL | ? | ? | 50 | 50 | ? | 100+ | 1st |
| engine-V | 50 | 50 | 0 | 0 | ? | 100+ | 2nd |
| Reindeer | ? | 60+ | 3rd | ||||
| SERV | na | na | na | na | ? | ? | Special Prize |
| Design | LC/FabLUT | DSP | EBR | SPRAM | Boot |
|---|---|---|---|---|---|
| engine-V | 307/280 | 0 | 4 | 1 | SPI bootstrap |
| spinalHDL | 1610/ | 0 | 4 | 2 | SPI XiP |
| SERV | ?/460+ | 0 | ? | ? | ? |
| fwrisc | 1653/? | 0 | 4 | ? | ? |
| glacial | /220+ | 0 | 0 | 2? | multiboot? |
| Design | LE/FabLUT | DSP | SRAM u/L/e | eNVM | Boot |
|---|---|---|---|---|---|
| engine-V | 346/268 | 0 | 1/1/0.4 | + | M3 |
| fwrisc | ?/1060 | 0 | 2/0/? | ? | ? |
LE is Logic Elements FabLUT is actual number of LUT's used (excludes Interface LUT's)
| Design | Slices | LUT | BRAM |
|---|---|---|---|
| engine-V | 52 | 187 | 8.5 |
| glacial | 53 | 132 | 16 |
Xilinx FPGA was not target for the contest.
| Design | Dhrystone | DMIPS | CPU MHz | DMIPS/MHz | Boot |
|---|---|---|---|---|---|
| spinalHDL | 65532 | 27 | 1.38 | SPI XiP | |
| Reindeer | 10704 | 24 | UART |
| Design | Dhrystone | DMIPS | CPU MHz | DMIPS/MHz | Boot |
|---|---|---|---|---|---|
| spinalHDL | 276695 | 114 | 1.38 | SPI XiP | |
| Reindeer | 81967 | 160 | UART |