diff --git a/.gitignore b/.gitignore index 1c9afcab..695e4b9f 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,4 @@ bazel-*/ bazel-* +MODULE.bazel +MODULE.bazel.lock diff --git a/dependency_support/com_google_skywater_pdk/build_defs.bzl b/dependency_support/com_google_skywater_pdk/build_defs.bzl index f9ee1b70..0277a4e8 100644 --- a/dependency_support/com_google_skywater_pdk/build_defs.bzl +++ b/dependency_support/com_google_skywater_pdk/build_defs.bzl @@ -74,13 +74,19 @@ def _skywater_cell_library_impl(ctx): open_road_configuration = ctx.attr.openroad_configuration[OpenRoadPdkInfo] cell_lef_files = [lef_file for lef_file in ctx.files.srcs if lef_file.extension == "lef"] + if not cell_lef_files: + fail("No cell lef files found in " + str(ctx.files.srcs)) platform_gds_files = [gds_file for gds_file in ctx.files.srcs if gds_file.extension == "gds"] + if not platform_gds_files: + fail("No gds files found in " + str(ctx.files.srcs)) tech_lef = None if ctx.attr.tech_lef: tech_lef = ctx.file.tech_lef - default_corner = corners.get(ctx.attr.default_corner, None) + default_corner = corners.get(ctx.attr.default_corner) + if not default_corner: + fail("Did not find the default corner provided:" + str(ctx.attr.default_corner)) default_lib_depset = [] if default_corner: default_lib_depset = [default_corner.liberty] diff --git a/dependency_support/com_google_skywater_pdk/cell_libraries.bzl b/dependency_support/com_google_skywater_pdk/cell_libraries.bzl index 9d0ae48a..5b25c1f6 100644 --- a/dependency_support/com_google_skywater_pdk/cell_libraries.bzl +++ b/dependency_support/com_google_skywater_pdk/cell_libraries.bzl @@ -26,11 +26,13 @@ CELL_LIBRARIES = { "commit": "7ec511f1a4689e174c63b3964d1ba8da9a3565e5", # v0.2.1, 2020-12-09 "shallow_since": "1606239275 -0800", "library_type": "ip_library", + "corners": {}, }, "sky130_fd_pr": { "commit": "f62031a1be9aefe902d6d54cddd6f59b57627436", # v0.20.1, 2020-12-09 "shallow_since": "1605038979 -0800", "library_type": "ip_library", + "corners": {}, }, "sky130_fd_sc_hd": { "commit": "ac7fb61f06e6470b94e8afdf7c25268f62fbd7b1", # v0.0.2, 2020-12-04 @@ -123,20 +125,20 @@ CELL_LIBRARIES = { "ff_n40C_5v50": ["basic", "ccsnoise"], "ff_n40C_5v50_lowhv1v65_lv1v95": ["basic"], "ff_n40C_5v50_lv1v95": ["basic", "ccsnoise"], - "hvff_lvss_100C_5v50_lowhv1v65_lv1v60": ["basic"], - "hvff_lvss_100C_5v50_lv1v40": ["basic"], - "hvff_lvss_100C_5v50_lv1v60": ["basic"], - "hvff_lvss_n40C_5v50_lowhv1v65_lv1v60": ["basic"], - "hvff_lvss_n40C_5v50_lv1v35": ["basic"], - "hvff_lvss_n40C_5v50_lv1v60": ["basic"], - "hvss_lvff_100C_1v65": ["basic"], - "hvss_lvff_100C_1v95": ["basic"], - "hvss_lvff_100C_1v95_lowhv1v65": ["basic"], - "hvss_lvff_100C_5v50_lowhv1v65_lv1v95": ["basic"], - "hvss_lvff_n40C_1v65": ["basic"], - "hvss_lvff_n40C_1v95": ["basic"], - "hvss_lvff_n40C_1v95_lowhv1v65": ["basic"], - "hvss_lvff_n40C_5v50_lowhv1v65_lv1v95": ["basic"], + #"hvff_lvss_100C_5v50_lowhv1v65_lv1v60": ["basic"], + #"hvff_lvss_100C_5v50_lv1v40": ["basic"], + #"hvff_lvss_100C_5v50_lv1v60": ["basic"], + #"hvff_lvss_n40C_5v50_lowhv1v65_lv1v60": ["basic"], + #"hvff_lvss_n40C_5v50_lv1v35": ["basic"], + #"hvff_lvss_n40C_5v50_lv1v60": ["basic"], + #"hvss_lvff_100C_1v65": ["basic"], + #"hvss_lvff_100C_1v95": ["basic"], + #"hvss_lvff_100C_1v95_lowhv1v65": ["basic"], + #"hvss_lvff_100C_5v50_lowhv1v65_lv1v95": ["basic"], + #"hvss_lvff_n40C_1v65": ["basic"], + #"hvss_lvff_n40C_1v95": ["basic"], + #"hvss_lvff_n40C_1v95_lowhv1v65": ["basic"], + #"hvss_lvff_n40C_5v50_lowhv1v65_lv1v95": ["basic"], "ss_100C_1v65": ["basic"], "ss_100C_1v65_lv1v40": ["basic"], "ss_100C_1v65_lv1v60": ["basic"], @@ -150,7 +152,7 @@ CELL_LIBRARIES = { "ss_150C_1v65_lv1v60": ["basic"], "ss_150C_3v00_lowhv1v65_lv1v60": ["basic"], "ss_n40C_1v32": ["basic"], - "ss_n40C_1v32_lv1v28": ["basic"], + #"ss_n40C_1v32_lv1v28": ["basic"], "ss_n40C_1v49": ["basic"], "ss_n40C_1v49_lv1v44": ["basic"], "ss_n40C_1v65": ["basic", "ccsnoise"], @@ -159,13 +161,13 @@ CELL_LIBRARIES = { "ss_n40C_1v65_lv1v60": ["basic", "ccsnoise"], "ss_n40C_1v95": ["basic"], "ss_n40C_5v50_lowhv1v65_lv1v60": ["basic"], - "tt_025C_2v64_lv1v80": ["basic"], - "tt_025C_2v97_lv1v80": ["basic"], + #"tt_025C_2v64_lv1v80": ["basic"], + #"tt_025C_2v97_lv1v80": ["basic"], "tt_025C_3v30": ["basic"], - "tt_025C_3v30_lv1v80": ["basic"], + #"tt_025C_3v30_lv1v80": ["basic"], "tt_100C_3v30": ["basic"], - "tt_100C_3v30_lv1v80": ["basic"], - "tt_150C_3v30_lv1v80": ["basic"], + #"tt_100C_3v30_lv1v80": ["basic"], + #"tt_150C_3v30_lv1v80": ["basic"], }, "default_corner": "ss_100C_1v95", }, @@ -195,11 +197,11 @@ CELL_LIBRARIES = { "shallow_since": "1604476021 -0800", "corners": { "ff_085C_1v95": ["basic"], - "ff_100C_1v65_dest1v76_destvpb1v76_ka1v76": ["basic"], + #"ff_100C_1v65_dest1v76_destvpb1v76_ka1v76": ["basic"], "ff_100C_1v95": ["basic"], "ff_150C_1v95": ["basic"], "ff_n40C_1v56": ["basic"], - "ff_n40C_1v65_dest1v76_destvpb1v76_ka1v76": ["basic"], + #"ff_n40C_1v65_dest1v76_destvpb1v76_ka1v76": ["basic"], "ff_n40C_1v76": ["basic"], "ff_n40C_1v95": ["basic", "ccsnoise"], "ss_100C_1v40": ["basic"], @@ -225,7 +227,7 @@ CELL_LIBRARIES = { "ff_100C_1v95": ["basic", "leakage"], "ff_150C_1v95": ["basic"], "ff_n40C_1v56": ["basic"], - "ff_n40C_1v65_ka1v76": ["basic"], + #"ff_n40C_1v65_ka1v76": ["basic"], "ff_n40C_1v76": ["basic"], "ff_n40C_1v95": ["basic", "ccsnoise", "leakage"], "ss_100C_1v60": ["basic"], diff --git a/dependency_support/com_google_skywater_pdk/cells_info.bzl b/dependency_support/com_google_skywater_pdk/cells_info.bzl new file mode 100644 index 00000000..01b0bd6a --- /dev/null +++ b/dependency_support/com_google_skywater_pdk/cells_info.bzl @@ -0,0 +1,150 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Standard cell options for SkyWater 130nm PDK.""" + +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cell_libraries.bzl", "CELL_LIBRARIES") +load("@rules_hdl//pdk:build_defs.bzl", "StandardCellOptionsInfo", "check_for_each_cells_args", "temp_normalize", "voltage_normalize") + +SKY130_OPTIONS = StandardCellOptionsInfo( + libraries = [ + "sc_hd", + #"sc_hdll", + #"sc_hs", + #"sc_ms", + #"sc_ls", + #"sc_lp", + #"sc_hvl", + ], + vts = [], + corners = list(sorted({ + cname.split("_")[0]: None + for libname in CELL_LIBRARIES + for cname in CELL_LIBRARIES[libname]["corners"] + }.keys())), + volts = list(sorted({ + voltage_normalize(cname.split("_")[2]): None + for libname in CELL_LIBRARIES + for cname in CELL_LIBRARIES[libname]["corners"] + }.keys())), + temps = list(sorted({ + temp_normalize(cname.split("_")[1]): None + for libname in CELL_LIBRARIES + for cname in CELL_LIBRARIES[libname]["corners"] + }.keys())), +) + +def sky130_cell_normalize(libname, corner_def): + """Normalize a corner name. + + Args: + libname: Name of the standard cell library (like `sc_hd`). + corner_def: Skywater corner definitions (like `ff_100C_1v65`). + + Returns: + The normalize name like `sky130-sc_hd-ff-0v123_m40c` + + """ + bits = corner_def.split("_") + corner, temp, voltage = bits[:3] + v_extra = '' + if len(bits) > 3: + v_extra += '_' + if bits[3].startswith('lowhv'): + v_extra += voltage_normalize(bits.pop(3)[6:])+'t' + if len(bits) > 3 and bits[3].startswith('lv'): + v_extra += 't'+voltage_normalize(bits.pop(3)[3:]) + if len(bits) > 3: + fail("Found extra bits in corner definition {} (from '{}')".format(bits[3:], corner_def)) + + temp = temp_normalize(temp) + voltage = voltage_normalize(voltage) + + return "sky130-{n}-{c}-{v}_{t}".format( + n = libname, + c = corner, + v = voltage+v_extra, + t = temp, + ) + +def for_each_sky130_cells(libname, include_vts = None, include_corners = None, include_volts = None, include_temps = None): + """Generate a list of each standard cell library name. + + Args: + libname: Libaray name like 'sc_hd'. + include_vts: Unused for sky130. + include_corners: 'all' or list of corners ('ff', 'tt', 'ss') to include in the output. + include_volts: 'all' or list of voltages (in '0p55v' form) to include in the output. + include_temps: 'all' or list of temperatures (in 'm40c' or '125c' form) to include in the output. + + Returns: + A list of tuples containing a unique name for the cell library + (suitable for usage in rule names) and the bazel target for the cell + library. + + Example: + ``` + [ + ("sky130-sc_hd-ff-0p605_125c", "@com_google_skywater_pdk_sky130_fd_sc_hd//:sky130-sc_hd-ff-0p605_125c"), + ("sky130-sc_hd-ff-0p605_m40c", "@com_google_skywater_pdk_sky130_fd_sc_hd//:sky130-sc_hd-ff-0p605_m40c"), + .... + ] + ``` + + Use this to create bazel rules for every standard cell version like shown below; + ``` + load("@rules_hdl//dependency_support/com_google_skywater_pdk:build_info.bzl", "for_each_sky130_cells") + [ + extract_lef_and_liberty( + name = cell_name + "-data", + standard_cell = cell_target, + ) + for cell_name, cell_target in for_each_sky130_cells('sc_hd', include_corners=['25c']) + ] + ``` + """ + kwargs = { + "libname": libname, + "include_vts": include_vts, + "include_corners": include_corners, + "include_volts": include_volts, + "include_temps": include_temps, + } + check_for_each_cells_args(kwargs, SKY130_OPTIONS) + + # Iterate over all the options, skipping values not found in the include_XXX arguments. + corners = {} + for corner_def in CELL_LIBRARIES["sky130_fd_" + libname]["corners"]: + corner, temp, voltage = corner_def.split("_", 3) + + temp = temp_normalize(temp) + + if "_" in voltage: + voltage = voltage.split("_")[0] + voltage = voltage_normalize(voltage) + + if corner not in kwargs["include_corners"]: + continue + + if voltage not in kwargs["include_volts"]: + continue + + if temp not in kwargs["include_temps"]: + continue + + cell_name = sky130_cell_normalize(libname, corner_def) + cell_target = "@com_google_skywater_pdk_sky130_fd_{l}//:{c}".format(l = libname, c = cell_name) + corners[cell_name] = cell_target + + return list(sorted(corners.items())) diff --git a/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl b/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl index fbb7ceb7..4d8b891e 100644 --- a/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl +++ b/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl @@ -41,6 +41,8 @@ def com_google_skywater_pdk(): for library_name in CELL_LIBRARIES: library = CELL_LIBRARIES[library_name] + if library.get('library_type', None) == 'ip_library': + continue workspace_name = "com_google_skywater_pdk_" + library_name maybe( new_git_repository, diff --git a/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl b/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl index 0889d29f..0bb6f8c7 100644 --- a/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl +++ b/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl @@ -16,6 +16,7 @@ cell library workspace to set things up.""" load("@rules_hdl//dependency_support/com_google_skywater_pdk:build_defs.bzl", "skywater_cell_library", "skywater_corner") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "sky130_cell_normalize") load(":cell_libraries.bzl", "CELL_LIBRARIES") def declare_cell_library(workspace_name, name): @@ -32,13 +33,21 @@ def declare_cell_library(workspace_name, name): ) library = CELL_LIBRARIES[name] corners = library.get("corners", {}) + all_corners = [] for corner in corners: + target_name = sky130_cell_normalize(name, corner).replace("sky130_fd_", "") + corner_name = "corner-" + target_name + all_corners.append(corner_name) + # boolean values indicating ccsnoise and leakage information in this # corner. ccsnoise = "ccsnoise" in corners[corner] leakage = "leakage" in corners[corner] + + # Create the corner configuration skywater_corner( - name = "{}".format(corner), + name = corner_name, + corner = corner, visibility = ["//visibility:private"], srcs = native.glob([ "cells/**/*.lib.json", @@ -49,6 +58,37 @@ def declare_cell_library(workspace_name, name): with_leakage = leakage, standard_cell_root = "external/{}".format(workspace_name), ) + + # Library with only just a single corner. + skywater_cell_library( + name = target_name, + srcs = native.glob( + include = [ + "cells/**/*.lef", + "cells/**/*.gds", + ], + # There are two types of lefs in the PDK. One for magic a layout + # tool that requires some different properties set in the LEF that + # are not always suitable for the downstream tools like OpenROAD + # and yosys. We're basically just choosing that we want the normal + # lefs instead of the magic ones. + # + # Currently this repo doesn't integrate magic into the flow. At + # some point it will, and we'll need to somehow have both lefs, or + # fix the lefs upstream. Just know that you may at some point in the + # future need to modify this. + exclude = [ + "cells/**/*.magic.lef", + ], + ), + process_corners = [":" + corner_name], + default_corner = corner, + visibility = ["//visibility:public"], + openroad_configuration = library.get("open_road_configuration", None), + tech_lef = "tech/{}.tlef".format(name) if library.get("library_type", None) != "ip_library" else None, + ) + + # Multi-corner library skywater_cell_library( name = name, srcs = native.glob( @@ -70,7 +110,7 @@ def declare_cell_library(workspace_name, name): "cells/**/*.magic.lef", ], ), - process_corners = [":{}".format(corner) for corner in corners], + process_corners = [":{}".format(corner) for corner in all_corners], default_corner = library.get("default_corner", ""), visibility = ["//visibility:public"], openroad_configuration = library.get("open_road_configuration", None), diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cells_info.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cells_info.bzl new file mode 100644 index 00000000..250d84fd --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cells_info.bzl @@ -0,0 +1,111 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Standard cell options for the ASAP7 7nm predictive PDK.""" + +load("@rules_hdl//pdk:build_defs.bzl", "StandardCellOptionsInfo", "check_for_each_cells_args") + +ASAP7_OPTIONS = StandardCellOptionsInfo( + libraries = [ + "sc6t_rev26", + "sc7p5t_rev27", + "sc7p5t_rev28", + ], + vts = [ + "rvt", # Regular VT -- Slowest + "lvt", # Low VT + "slvt", # Super low VT -- Fastest + ], + corners = [ + "ff", + "tt", + "ss", + ], + volts = [ + # ??? + ], + temps = [ + # ??? + ], +) + +def for_each_asap7_cells(libname, include_vts = None, include_corners = None, include_volts = None, include_temps = None): + """Generate a list of each standard cell library name. + + Args: + libname: Libaray name like 'h169l3p48'. + include_vts: 'all' or list of vts ('rvt', 'lvt', 'slvt') to include in the output. + include_corners: 'all' or list of corners ('ff', 'tt', 'ss') to include in the output. + include_volts: 'all' or list of voltages (in '0p55v' form) to include in the output. + include_temps: 'all' or list of temperatures (in 'm40c' or '125c' form) to include in the output. + + Returns: + A list of tuples containing a unique name for the cell library + (suitable for usage in rule names) and the bazel target for the cell + library. + + Example: + ``` + [ + ('asap7-sc7p5t_rev27_rvt-ccs_ss', '@org_theopenroadproject_asap7sc7p5t_27//:asap7-sc7p5t_rev27_rvt-ccs_ss'), + ('asap7-sc7p5t_rev27_lvt-ccs_ss', '@org_theopenroadproject_asap7sc7p5t_27//:asap7-sc7p5t_rev27_lvt-ccs_ss'), + ... + ] + ``` + Use this to create bazel rules for every standard cell version like shown below; + ``` + load("//hardware/tools/open_road/asap7:build_info.bzl", "for_each_asap7_cells") + [ + extract_lef_and_liberty( + name = cell_name+"-data", + standard_cell = cell_target, + ) + for cell_name, cell_target in for_each_asap7_cells('sc7p5t_rev28', include_corners=['25c']) + ] + ``` + """ + kwargs = { + "libname": libname, + "include_vts": include_vts, + "include_corners": include_corners, + "include_volts": include_volts, + "include_temps": include_temps, + } + check_for_each_cells_args(kwargs, ASAP7_OPTIONS) + + # Iterate over all the options, skipping values not found in the include_XXX arguments. + output = [] + for vt in ASAP7_OPTIONS.vts: + if vt not in kwargs["include_vts"]: + continue + + for corner in ASAP7_OPTIONS.corners: + if corner not in kwargs["include_corners"]: + continue + + # No voltage or temps for ASAP7 + + # asap7-sc7p5t_rev27_rvt_4x + cell_name = "asap7-{n}_{v}-ccs_{c}".format( + n = libname, + v = vt, + c = corner, + ) + + libname_short = libname.replace("rev", "") + + # "@org_theopenroadproject_asap7sc7p5t_27//:asap7-sc7p5t_rev27_rvt-ccs_ss + cell_target = "@org_theopenroadproject_asap7{}//:{}".format(libname_short, cell_name) + output.append((cell_name, cell_target)) + return output diff --git a/flows/asap7.bzl b/flows/asap7.bzl deleted file mode 100644 index 258b998a..00000000 --- a/flows/asap7.bzl +++ /dev/null @@ -1,104 +0,0 @@ -# Copyright 2021-2022 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" Macro for quick ASAP7 basic flow. """ - -load("@bazel_skylib//rules:build_test.bzl", "build_test") -load("//gds_write:build_defs.bzl", "gds_write") -load("//place_and_route:build_defs.bzl", "place_and_route") -load("//static_timing:build_defs.bzl", "run_opensta") -load("//synthesis:build_defs.bzl", "synthesize_rtl") - -def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20, corners = ("ccs_ss", "ccs_tt", "ccs_ff")): - """Generate targets for a quick basic ASAP7 flow. - - Args: - name: Name for the macro instance. - target: Verilog library name. - rev: ASAP7 revision (26 / 27 / 28). - tracks: Number of tracks ("7p5t", "6t"). - vt: VT type ("rvt", "lvt", "slvt"). - has_gds: Cells have GDS layouts. - size: Size of the die in microns. - corners: List of corners to generate rules for (default is `ccs_ss`, `ccs_tt`, `ccs_ff`). - """ - if rev not in [26, 27, 28]: - fail("Invalid rev {}".format(repr(rev))) - if tracks not in ["7p5t", "6t"]: - fail("Invalid rev {}".format(repr(tracks))) - - # TODO: Add the NLDM support once it works with OpenROAD. - for corner in corners: - a = { - "name": target, - "tracks": tracks, - "rev": rev, - "vt": vt, - "corn": corner, - } - - synthesize_rtl( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}-{corn}".format(**a), - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":{name}".format(**a), - ], - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ], - ) - - run_opensta( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a), - synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ], - ) - - place_and_route( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - core_padding_microns = 1, - die_height_microns = size, - die_width_microns = size, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - ], - ) - - if has_gds: - gds_write( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), - implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), - ], - ) diff --git a/flows/basic_asic.bzl b/flows/basic_asic.bzl new file mode 100644 index 00000000..165a695b --- /dev/null +++ b/flows/basic_asic.bzl @@ -0,0 +1,130 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Very basic ASIC flow, mainly used for testing and debugging.""" + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("//gds_write:build_defs.bzl", "gds_write") +load("//place_and_route:build_defs.bzl", "place_and_route") +load("//static_timing:build_defs.bzl", "run_opensta") +load("//synthesis:build_defs.bzl", "synthesize_rtl") + +def _get_with_defaults(target_name, extra_args, defaults): + target_extra_args = dict(**extra_args.pop(target_name, {})) + for k, v in defaults.items(): + if k not in target_extra_args: + target_extra_args[k] = v + return target_extra_args + +def basic_asic_flow(name, target, cells, top = None, extra_args = {}, gds = True, size = 20): + """Generate targets for a basic ASIC flow. + + Args: + name: Name for the macro instance. + target: Verilog library name. + cells: Standard cells to use. + top: Name of the top level module (defaults to name). + gds: Run all the way to GDS output. + extra_args: Extra arguments to provide the steps in the flow. + size: Size of the die in microns. + """ + if top == None: + top = name + extra_args = dict(**extra_args) + + # Synthesis + synthesize_rtl( + name = name + "-step1-synth", + standard_cells = cells, + top_module = top, + deps = [ + target, + ], + **_get_with_defaults( + "synthesize_rtl", + extra_args, + dict( + target_clock_period_pico_seconds = 10000, + ), + ) + ) + build_test( + name = "build-" + name + "-step1-synth", + targets = [":" + name + "-step1-synth"], + ) + + # Static timing analysis of synthesis result + run_opensta( + name = name + "-step1-synth_sta", + synth_target = ":" + name + "-step1-synth", + **_get_with_defaults( + "synth_run_opensta", + extra_args, + dict( + # No defaults at the moment. + ), + ) + ) + build_test( + name = "build-" + name + "-step1-synth_sta", + targets = [":" + name + "-step1-synth_sta"], + ) + + # Place and Route + place_and_route( + name = name + "-step2-place_and_route", + synthesized_rtl = ":" + name + "-step1-synth", + **_get_with_defaults( + "place_and_route", + extra_args, + dict( + placement_density = "0.65", + core_padding_microns = 1, + die_height_microns = size, + die_width_microns = size, + ), + ) + ) + build_test( + name = "build-" + name + "-step2-place_and_route", + targets = [ + ":" + name + "-step2-place_and_route", + ], + ) + + # FIXME: Should add a post place and route run_opensta? + + # GDS Generation + if gds: + gds_write( + name = name + "-step3-gds", + implemented_rtl = ":" + name + "-step2-place_and_route", + **_get_with_defaults( + "gds_write", + extra_args, + dict( + # No defaults at the moment. + ), + ) + ) + build_test( + name = "build-" + name + "-step3-gds", + targets = [ + ":" + name + "-step3-gds", + ], + ) + + # Make sure everything in the extra_args dictionary has been used. + if extra_args: + fail("{} provided in 'extra_args' was not used, please remove.".format("and ".join(extra_args.keys()))) diff --git a/pdk/build_defs.bzl b/pdk/build_defs.bzl index 75f5d46a..3a6fcbf4 100644 --- a/pdk/build_defs.bzl +++ b/pdk/build_defs.bzl @@ -12,8 +12,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""Providers for PDKs to be used by downstream synthesis. -""" +"""Providers for PDKs to be used by downstream synthesis.""" StandardCellInfo = provider( "Contains information about the standard cells used for synthesis", @@ -38,3 +37,280 @@ CornerInfo = provider( "corner_name": "Name of the process corner", }, ) + +StandardCellOptionsInfo = provider( + "Provides information about what standard cell options are available", + fields = { + "libraries": "A list of available standard cell library names.", + "vts": "A list of voltage thresholds names.", + "corners": "A list of valid corners names.", + "volts": "A list of (normalize) voltage levels names used in timing characterization.", + "temps": "A list of (normalize) temperature values names used in timing characterization.", + }, +) + +def temp_format(i): + """Format an integer representing degrees celsius. + + Args: + i: Temperature as integer in degrees celsius. + + Returns: + A formated string version of input. + + The format is: + * Always 4 characters long. + * Always ends in lower case 'c'. + * Negative values start with lower case `m`. + * Left padded by zeros. + + The format can represent whole (integer) degrees between (inclusive) 999C to -99C. + + The format is designed to have sort in a decent way as a string. + + >>> voltage_format(30) + "030c" + + >>> voltage_format(-10) + "m10c" + + >>> voltage_format(0) + "000c" + + """ + if i < -99 or i > 999: + fail("Temperature value {} out side range for formatting (-99 -> 999).".format(i)) + + if i < -10: + s = "m" + str(i)[1:] + elif i < 0: + s = "m0" + str(i)[1:] + elif i < 10: + s = "00" + str(i) + elif i < 100: + s = "0" + str(i) + else: + s = str(i) + + return s + "c" + +def temp_parse(s): + """Parse a string representing temperature in degrees celsius into integer. + + Args: + s: Temperature as string. + + Returns: + An integer representing temperature in degrees celsius. + + >>> temp_parse("030c") + 30 + + >>> temp_parse("000c") + 0 + + >>> temp_parse("m35c") + -35 + + >>> temp_parse("n35c") + -35 + + >>> temp_parse("0c") + 0 + + >>> temp_parse("m02c") + -2 + + """ + os = s + s = s.lower().strip() + + # Check string ends in `c` (for degree celsius) + if s[-1] != "c": + fail("No `c` character found at end of value {} (input {})".format(s, os)) + s = s[:-1] + + # Convert `m` into negative sign + if s.startswith("n"): + s = "m" + s[1:] + + m = 1 + if s.startswith("m"): + m = -1 + s = s[1:] + + # Trim leading zeros + if s[:-1].startswith("0"): + s = s[:-1].lstrip("0") + s[-1] + + return int(s) * m + +def temp_normalize(s): + """Normalize an already existing temperature string into the format provided by `temp_format`. + + Args: + s: Temperature as string. + + Returns: + A normalize version of the input string. + + >>> temp_normalize("m2c") + "m02c" + + >>> temp_normalize("30c") + "030c" + + >>> voltage_format("0c") + "000c" + + >>> voltage_format("125c") + "125c" + """ + return temp_format(temp_parse(s)) + +def voltage_format(f): + """Format a decimal number representing a voltage. + + Args: + f: Voltage as decimal number (float / int). + + Returns: + A string version of the input. + + The format is: + * Always 5 characters long. + * Has one digit before the decimal point. + * Has three digital after the decimal point. + * Uses the character `p` for the decimal point. + + The format can represent voltages between (inclusive) 9.999 volts to 0.000 volts. + + The format is designed to have sort in a decent way as a string. + + >>> voltage_format(7.5) + "7v500" + + >>> voltage_format(0) + "0v000" + + >>> voltage_format(-10) + Failure... + + >>> voltage_format(2) + Failure... + + """ + if f >= 10 or f <= 0: + fail("Voltage value {} out side range for formatting (0.000 -> 9.999)".format(f)) + + # We really want `"{:1.3f}".format(f)` but starlark doesn't support it + s = str(f)[:5] + if len(s) < 5: + s = s + "0" * (5 - len(s)) + return s.replace(".", "v", 1) + +def voltage_normalize(s): + """Normalize an existing voltage string into the format provided by `voltage_format`. + + Args: + s: Voltage as string. + + Returns: + A normalize version of the input string. + + >>> voltage_normalize("7p5v") + "7v500" + + >>> voltage_normalize("7v5") + "7v500" + + >>> voltage_normalize("7.5v") + "7v500" + """ + return voltage_format(voltage_parse(s)) + +def voltage_parse(s): + """Parse a voltage string like that produced by `voltage_format` function. + + Args: + s: Voltage as string. + + Returns: + A float version of the input string. + + >>> voltage_parse("7p5") + 7.5 + + >>> voltage_parse("7p500") + 7.5 + + >>> voltage_parse("0.75v") + 7.5 + + >>> voltage_parse("0v75") + 7.5 + """ + s = s.lower().strip() + + if s.endswith("v"): + s = s[:-1].replace(".", "p") + if "v" in s: + s = s.replace("v", "p") + + if "p" not in s: + fail("No decimal point found in {}".format(s)) + + s = s.replace("p", ".") + + return float(s) + +def check_for_each_cells_args(kwargs, options): + """Function for checking the arguments provided to a `for_each_XXX_cells` function are valid. + + Args: + kwargs: Dictionary of keyword arguments provided to `for_each_XXX_cells` function. + options: A `StandardCellOptionsInfo` for the PDK. + """ + #if isinstance(options, StandardCellOptionsInfo): + # fail("options should be a `StandardCellOptionsInfo` object.") + + if kwargs["libname"] not in options.libraries: + fail("Invalid library name: " + kwargs["libname"]) + + # Validate the provided voltage threadholds + if kwargs["include_vts"] in ("all", None): + kwargs["include_vts"] = options.vts + + for vt in kwargs["include_vts"]: + if vt not in options.vts: + fail("Invalid vt: {} (from {})".format(vt, kwargs["include_vts"])) + + # Valid the provided corners + if kwargs["include_corners"] in ("all", None): + kwargs["include_corners"] = options.corners + + for corner in kwargs["include_corners"]: + if corner not in options.corners: + fail("Invalid corner: {} (from {})".format(corner, kwargs["include_corners"])) + + # Validate and normalize the provided volts values + if kwargs["include_volts"] in ("all", None): + kwargs["include_volts"] = list(options.volts) + + for i, voltage in enumerate(kwargs["include_volts"]): + kwargs["include_volts"][i] = voltage_normalize(voltage) + + for voltage in kwargs["include_volts"]: + if voltage not in options.volts: + fail("Invalid volts: {} (from {})".format(voltage, kwargs["include_volts"])) + + # Validate and normalize the provided temperature values + if kwargs["include_temps"] in ("all", None): + kwargs["include_temps"] = list(options.temps) + + for i, temp in enumerate(kwargs["include_temps"]): + kwargs["include_temps"][i] = temp_normalize(temp) + + for temp in kwargs["include_temps"]: + if temp not in options.temps: + fail("Invalid temp: {} (from {})".format(temp, kwargs["include_temps"])) diff --git a/pdk/proto/build_defs.bzl b/pdk/proto/build_defs.bzl index 00f29777..c50c5fa7 100644 --- a/pdk/proto/build_defs.bzl +++ b/pdk/proto/build_defs.bzl @@ -19,6 +19,9 @@ def _extract_lef_and_liberty_impl(ctx): content.append("tech_lef_path: \"{}\"".format(standard_cell.tech_lef.short_path)) out_files.append(standard_cell.tech_lef) + if not standard_cell.default_corner: + fail("No default corner found on " + str(ctx.attr.standard_cell)) + content.append("liberty_path: \"{}\"".format(standard_cell.default_corner.liberty.short_path)) out_files.append(standard_cell.default_corner.liberty) else: diff --git a/place_and_route/build_defs.bzl b/place_and_route/build_defs.bzl index d6412dec..b749e194 100644 --- a/place_and_route/build_defs.bzl +++ b/place_and_route/build_defs.bzl @@ -105,6 +105,6 @@ place_and_route = rule( "sink_clustering_size": attr.int(doc = "Clock tree synthesis sink group size"), "sink_clustering_max_diameter": attr.int(doc = "Clock tree synthesis sink group desired diamater in microns"), "min_pin_distance": attr.string(doc = "The minimum distance in microns between pins around the outside of the block."), - "enable_improve_placement": attr.bool(default=True, doc = "Enable/Disable improve_placement pass.") + "enable_improve_placement": attr.bool(default = True, doc = "Enable/Disable improve_placement pass."), }, ) diff --git a/place_and_route/private/detailed_routing.bzl b/place_and_route/private/detailed_routing.bzl index b6f92fb3..fe1ca116 100644 --- a/place_and_route/private/detailed_routing.bzl +++ b/place_and_route/private/detailed_routing.bzl @@ -57,7 +57,7 @@ def detailed_routing(ctx, open_road_info): open_road_commands = timing_setup_command_struct.commands + [ "set_propagated_clock [all_clocks]", - "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args) + "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args), ] density_fill_config = None if open_road_configuration.density_fill_config: diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD deleted file mode 100644 index dc08b83d..00000000 --- a/synthesis/tests/BUILD +++ /dev/null @@ -1,183 +0,0 @@ -# Copyright 2021-2022 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -load("@bazel_skylib//rules:build_test.bzl", "build_test") -load("//flows:asap7.bzl", "asap7_targets") -load("//gds_write:build_defs.bzl", "gds_write") -load("//place_and_route:build_defs.bzl", "place_and_route") -load("//static_timing:build_defs.bzl", "run_opensta") -load("//synthesis:build_defs.bzl", "synthesize_rtl") -load("//verilog:providers.bzl", "verilog_library") - -package( - default_applicable_licenses = ["//:package_license"], - default_visibility = ["//visibility:private"], -) - -synthesize_rtl( - name = "verilog_adder_synthesized", - top_module = "adder", - deps = [ - ":verilog_adder", - ], -) - -verilog_library( - name = "verilog_adder", - srcs = [ - "verilog_adder.v", - ], -) - -########################################################################## -# Verilog counter -########################################################################## -verilog_library( - name = "verilog_counter", - srcs = [ - "counter.v", - ], -) - -# generic - -synthesize_rtl( - name = "verilog_counter-synth", - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-synth_sta", - synth_target = ":verilog_counter-synth", -) - -place_and_route( - name = "verilog_counter-place_and_route", - clock_period = "10", - core_padding_microns = 20, - die_height_microns = 200, - die_width_microns = 200, - placement_density = "0.7", - synthesized_rtl = ":verilog_counter-synth", -) - -gds_write( - name = "verilog_counter-gds", - implemented_rtl = ":verilog_counter-place_and_route", -) - -build_test( - name = "build-verilog_counter", - targets = [ - ":verilog_counter", - ":verilog_counter-synth", - ":verilog_counter-synth_sta", - ":verilog_counter-place_and_route", - ":verilog_counter-gds", - ], -) - -# ASAP7 7.5 track rev 28 -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev28_rvt", - rev = 28, - target = "verilog_counter", - tracks = "7p5t", - vt = "rvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev28_lvt", - rev = 28, - target = "verilog_counter", - tracks = "7p5t", - vt = "lvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev28_slvt", - rev = 28, - target = "verilog_counter", - tracks = "7p5t", - vt = "slvt", -) - -# ASAP7 7.5 track rev 27 -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt", - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "rvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_lvt", - has_gds = False, # No GDS for rev27 LVT - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "lvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_slvt", - has_gds = False, # No GDS for rev27 LVT - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "slvt", -) - -# ASAP7 7.5 track rev 27 4x scaled version -# FIXME: Enable the 4x scaled 7.5 track config. -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x", - size = 2000, - corners = ["ccs_ss"], - has_gds = False, # No GDS for the 4x cells - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "rvt_4x", -) - -# ASAP7 6 track rev 26 -# FIXME: Enable the 6 track config. -#asap7_targets( -# name = "verilog_counter-asap7-6t_rev26_rvt", -# rev = 26, -# target = "verilog_counter", -# tracks = "6t", -# vt = "rvt", -#) -# -#asap7_targets( -# name = "verilog_counter-asap7-6t_rev26_lvt", -# rev = 26, -# target = "verilog_counter", -# tracks = "6t", -# vt = "lvt", -#) -# -#asap7_targets( -# name = "verilog_counter-asap7-6t_rev26_slvt", -# rev = 26, -# target = "verilog_counter", -# tracks = "6t", -# vt = "slvt", -#) diff --git a/tests/BUILD b/tests/BUILD new file mode 100644 index 00000000..bfe56e85 --- /dev/null +++ b/tests/BUILD @@ -0,0 +1,203 @@ +# Copyright 2021-2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//gds_write:build_defs.bzl", "gds_write") +load("//place_and_route:build_defs.bzl", "place_and_route") +load("//static_timing:build_defs.bzl", "run_opensta") +load("//synthesis:build_defs.bzl", "synthesize_rtl") +load("//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +########################################################################## +# Basic tests of individual steps in the ASIC flow. +########################################################################## +BASIC_TESTS = [ + "verilog_adder", + "verilog_counter", +] + +# Basic `verilog_library` test +[ + verilog_library( + name = test_name, + srcs = [ + test_name + ".v", + ], + ) + for test_name in BASIC_TESTS +] + +# Basic `synthesize_rtl` test +[ + synthesize_rtl( + name = test_name + "-synth", + top_module = test_name, + deps = [ + ":" + test_name, + ], + ) + for test_name in BASIC_TESTS +] + +# Basic `run_opensta` test (on output of `synthesize_rtl`) +[ + run_opensta( + name = test_name + "-synth_sta", + synth_target = ":" + test_name + "-synth", + ) + for test_name in BASIC_TESTS +] + +# Basic `place_and_route` test (on output of `synthesize_rtl`) +place_and_route( + name = "verilog_adder-place_and_route", + clock_period = None, # Combinational only design + core_padding_microns = 20, + die_height_microns = 200, + die_width_microns = 200, + placement_density = "0.7", + synthesized_rtl = ":verilog_adder-synth", +) + +place_and_route( + name = "verilog_counter-place_and_route", + clock_period = "10", + core_padding_microns = 20, + die_height_microns = 200, + die_width_microns = 200, + placement_density = "0.7", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-synth", +) + +# Basic `gds_write` test (on output of `place_and_route`) +[ + gds_write( + name = test_name + "-gds", + implemented_rtl = ":" + test_name + "-place_and_route", + ) + for test_name in BASIC_TESTS +] + +# Make sure that all the basic tests above actually build +[ + build_test( + name = "build-" + test_name, + targets = [ + ":" + test_name, + ":" + test_name + "-synth", + ":" + test_name + "-synth_sta", + ":" + test_name + "-place_and_route", + ":" + test_name + "-gds", + ], + ) + for test_name in BASIC_TESTS +] + +########################################################################## +# Basic tests which run for each standard cell library. +########################################################################## + +EXTRA_ARGS = { + "verilog_counter": { + "place_and_route": dict( + sdc = "constraint.sdc", + ), + }, + "verilog_adder": { + "place_and_route": dict( + clock_period = None, # Combinational only design + ), + }, +} + +# SkyWater 130nm PDK +# ------------------------------------------------------------------------ +# Skywater 130nm PDK - High Density standard cells +[ + [ + basic_asic_flow( + name = test_name + "-" + cell_name, + size = 200, + cells = cell_target, + extra_args = EXTRA_ARGS[test_name], + target = ":" + test_name, + top = test_name, + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") + ] + for test_name in BASIC_TESTS +] + +# FIXME: Add other ('sc_hs', 'sc_ms', 'sc_ls', ...) +# Skywater 130nm PDK - XXXXX standard cells + +# ASAP7 predictive 7nm PDK +# ------------------------------------------------------------------------ + +# FIXME: Add ASAP7 7nm PDK - 6 track rev 26 standard cells + +# ASAP 7nm PDK - 7.5 track rev 27 standard cells +[ + [ + basic_asic_flow( + name = test_name + "-" + cell_name, + cells = cell_target, + extra_args = EXTRA_ARGS[test_name], + gds = False, # No GDS for the rev 27 cells + target = ":" + test_name, + top = test_name, + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") + ] + for test_name in BASIC_TESTS +] + +# ASAP 7nm PDK - 7.5 track rev 28 standard cells +[ + [ + basic_asic_flow( + name = test_name + "-" + cell_name, + size = 20, + cells = cell_target, + extra_args = EXTRA_ARGS[test_name], + target = ":" + test_name, + top = test_name, + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") + ] + for test_name in BASIC_TESTS +] + +# "Special" ASAP7 7.5 track rev 27 4x scaled version +[ + basic_asic_flow( + name = test_name + "-asap7-sc7p5t_rev27_rvt_4x", + size = 2000, + cells = "@org_theopenroadproject_asap7sc7p5t_27//:asap7-sc7p5t_rev27_rvt_4x-ccs_ss", + extra_args = EXTRA_ARGS[test_name], + gds = False, # No GDS for the 4x cells + target = ":" + test_name, + top = test_name, + ) + for test_name in BASIC_TESTS +] diff --git a/synthesis/tests/constraint.sdc b/tests/constraint.sdc similarity index 93% rename from synthesis/tests/constraint.sdc rename to tests/constraint.sdc index 91a42270..8d22f28c 100644 --- a/synthesis/tests/constraint.sdc +++ b/tests/constraint.sdc @@ -1,4 +1,4 @@ -current_design counter +current_design verilog_counter set clk_name core_clock set clk_port_name clk diff --git a/synthesis/tests/verilog_adder.v b/tests/verilog_adder.v similarity index 97% rename from synthesis/tests/verilog_adder.v rename to tests/verilog_adder.v index 3ca319e5..3e945b2e 100644 --- a/synthesis/tests/verilog_adder.v +++ b/tests/verilog_adder.v @@ -13,7 +13,7 @@ //limitations under the License. -module adder( +module verilog_adder( input [7:0] x, input [7:0] y, input carry_in, diff --git a/synthesis/tests/counter.v b/tests/verilog_counter.v similarity index 97% rename from synthesis/tests/counter.v rename to tests/verilog_counter.v index 33d671ed..c826eabb 100644 --- a/synthesis/tests/counter.v +++ b/tests/verilog_counter.v @@ -13,7 +13,7 @@ //limitations under the License. -module counter( +module verilog_counter( input wire clk, input wire reset, output [128:0] out, diff --git a/tools/test_everything.py b/tools/test_everything.py index 6126fcd9..a8c1769d 100755 --- a/tools/test_everything.py +++ b/tools/test_everything.py @@ -43,8 +43,6 @@ '@com_google_skywater_pdk_sky130_fd_sc_hs//...', '@com_google_skywater_pdk_sky130_fd_sc_hdll//...', '@com_google_skywater_pdk_sky130_fd_sc_hd//...', - '@com_google_skywater_pdk_sky130_fd_pr//...', - '@com_google_skywater_pdk_sky130_fd_io//...', '@com_icarus_iverilog//...', '@com_opencircuitdesign_magic//...', '@com_opencircuitdesign_netgen//...', @@ -64,6 +62,8 @@ '@org_sourceware_libffi//...', '@org_swig//...', '@org_theopenroadproject_asap7_pdk_r1p7//...', + '@org_theopenroadproject_asap7sc6t_26//...', + '@org_theopenroadproject_asap7sc7p5t_27//...', '@org_theopenroadproject_asap7sc7p5t_28//...', '@pybind11//...', '@rules_pkg//...',