diff --git a/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD b/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD index 3c45c7a1..c7947207 100644 --- a/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD +++ b/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD @@ -49,4 +49,5 @@ open_road_pdk_configuration( ], wire_rc_clock_metal_layer = "met5", wire_rc_signal_metal_layer = "met2", + ha_fa_mapping = "cell_adders.v" ) diff --git a/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/cell_adders.v b/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/cell_adders.v new file mode 100644 index 00000000..b3a18dc0 --- /dev/null +++ b/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/cell_adders.v @@ -0,0 +1,49 @@ +// File copy form OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1 +// Works only with sky130_fd_sc_hd +(* techmap_celltype = "$fa" *) +module _tech_fa (A, B, C, X, Y); + parameter WIDTH = 1; + (* force_downto *) + input [WIDTH-1 : 0] A, B, C; + (* force_downto *) + output [WIDTH-1 : 0] X, Y; + + parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx; + + genvar i; + generate for (i = 0; i < WIDTH; i = i + 1) begin + if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + sky130_fd_sc_hd__ha_1 halfadder_Cconst ( + .A(A[i]), + .B(B[i]), + .COUT(X[i]), .SUM(Y[i]) + ); + end + else begin + if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin + sky130_fd_sc_hd__ha_1 halfadder_Bconst ( + .A(A[i]), + .B(C[i]), + .COUT(X[i]), .SUM(Y[i]) + ); + end + else begin + sky130_fd_sc_hd__ha_1 halfadder_Aconst ( + .A(B[i]), + .B(C[i]), + .COUT(X[i]), .SUM(Y[i]) + ); + end + end + end + else begin + sky130_fd_sc_hd__fa_1 fulladder ( + .A(A[i]), .B(B[i]), .CIN(C[i]), .COUT(X[i]), .SUM(Y[i]) + ); + end + end endgenerate + +endmodule diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/BUILD b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/BUILD index 31c94bec..db0f09a6 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/BUILD +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/BUILD @@ -25,4 +25,7 @@ exports_files([ "pdn_config_1x.pdn", # FIXME: Where did this come from? "pdn_config_4x.pdn", # FIXME: Where did this come from? "asap7.lyt", # Imported from OpenROAD-flow-scripts on 24.07.2023 at 6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8 from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8/flow/platforms/asap7/KLayout/asap7.lyt + "cell_adders_R.v", + "cell_adders_L.v", + "cell_adders_SL.v", ]) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_L.v b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_L.v new file mode 100644 index 00000000..a2d55d59 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_L.v @@ -0,0 +1,56 @@ +// File copy form +// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1 +// Only works with asap7 L cell library +(* techmap_celltype = "$fa" *) +module _tech_fa (A, B, C, X, Y); + parameter WIDTH = 1; + (* force_downto *) + input [WIDTH-1 : 0] A, B, C; + (* force_downto *) + output [WIDTH-1 : 0] X, Y; + + wire [WIDTH-1 : 0] NX, NY; + + parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx; + + genvar i; + generate for (i = 0; i < WIDTH; i = i + 1) begin + if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + HAxp5_ASAP7_75t_L halfadder_Cconst ( + .A(A[i]), + .B(B[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + else begin + if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin + HAxp5_ASAP7_75t_L halfadder_Bconst ( + .A(A[i]), + .B(C[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + else begin + HAxp5_ASAP7_75t_L halfadder_Aconst ( + .A(B[i]), + .B(C[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + end + end + else begin + FAx1_ASAP7_75t_L fulladder ( + .A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i]) + ); + end + + assign X[i] = ~NX[i]; + assign Y[i] = ~NY[i]; + + end endgenerate + +endmodule diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_R.v b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_R.v new file mode 100644 index 00000000..0f38f764 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_R.v @@ -0,0 +1,56 @@ +// File copy form +// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1 +// Only works with asap7 R cell library +(* techmap_celltype = "$fa" *) +module _tech_fa (A, B, C, X, Y); + parameter WIDTH = 1; + (* force_downto *) + input [WIDTH-1 : 0] A, B, C; + (* force_downto *) + output [WIDTH-1 : 0] X, Y; + + wire [WIDTH-1 : 0] NX, NY; + + parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx; + + genvar i; + generate for (i = 0; i < WIDTH; i = i + 1) begin + if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + HAxp5_ASAP7_75t_R halfadder_Cconst ( + .A(A[i]), + .B(B[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + else begin + if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin + HAxp5_ASAP7_75t_R halfadder_Bconst ( + .A(A[i]), + .B(C[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + else begin + HAxp5_ASAP7_75t_R halfadder_Aconst ( + .A(B[i]), + .B(C[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + end + end + else begin + FAx1_ASAP7_75t_R fulladder ( + .A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i]) + ); + end + + assign X[i] = ~NX[i]; + assign Y[i] = ~NY[i]; + + end endgenerate + +endmodule diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_SL.v b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_SL.v new file mode 100644 index 00000000..9c340bd3 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_SL.v @@ -0,0 +1,56 @@ +// File copy form +// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1 +// Only works with asap7 R cell library +(* techmap_celltype = "$fa" *) +module _tech_fa (A, B, C, X, Y); + parameter WIDTH = 1; + (* force_downto *) + input [WIDTH-1 : 0] A, B, C; + (* force_downto *) + output [WIDTH-1 : 0] X, Y; + + wire [WIDTH-1 : 0] NX, NY; + + parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx; + parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx; + + genvar i; + generate for (i = 0; i < WIDTH; i = i + 1) begin + if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin + HAxp5_ASAP7_75t_SL halfadder_Cconst ( + .A(A[i]), + .B(B[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + else begin + if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin + HAxp5_ASAP7_75t_SL halfadder_Bconst ( + .A(A[i]), + .B(C[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + else begin + HAxp5_ASAP7_75t_SL halfadder_Aconst ( + .A(B[i]), + .B(C[i]), + .CON(NX[i]), .SN(NY[i]) + ); + end + end + end + else begin + FAx1_ASAP7_75t_SL fulladder ( + .A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i]) + ); + end + + assign X[i] = ~NX[i]; + assign Y[i] = ~NY[i]; + + end endgenerate + +endmodule diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel index 12414162..bd563c50 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel @@ -103,6 +103,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) # From org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl @@ -162,6 +163,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) # From org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl @@ -287,6 +289,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) ########################################################################## @@ -349,6 +352,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) # From org_theopenroadproject_asap7sc7p5t_27/common.bzl diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl index 3afa1f1b..918405a9 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl @@ -68,4 +68,5 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl index 9b90eb3b..46260807 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl @@ -68,4 +68,5 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl index 6b31d614..b98c2ff5 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl @@ -134,6 +134,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) ########################################################################## diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl index ab220883..c59d5cde 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl @@ -68,4 +68,5 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel index d55e051c..76c81829 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel @@ -102,6 +102,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) # From org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl @@ -160,6 +161,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) # From org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl @@ -218,6 +220,7 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) # From org_theopenroadproject_asap7sc7p5t_28/common.bzl diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl index fb15ca25..b97bc556 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl @@ -67,4 +67,5 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl index 5d756478..ec10602a 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl @@ -67,4 +67,5 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl index b7f5270b..8b5a042a 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl @@ -67,4 +67,5 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) diff --git a/pdk/build_defs.bzl b/pdk/build_defs.bzl index 02f0c6d1..75f5d46a 100644 --- a/pdk/build_defs.bzl +++ b/pdk/build_defs.bzl @@ -23,6 +23,7 @@ StandardCellInfo = provider( "tech_lef": "Tech LEF file for the PDK", "cell_lef_definitions": "list of Abstract LEFs files for each standard cell.", "platform_gds": "list of Platform GDS files.", + "ha_fa_mapping": "HA/FA techmapping file", "parasitic_extraction_benchmark": "Optional calibration file for OpenRCX.", "open_road_configuration": "OpenROAD PDK configuration.", }, diff --git a/pdk/open_road_configuration.bzl b/pdk/open_road_configuration.bzl index 88b6450f..29ceb232 100644 --- a/pdk/open_road_configuration.bzl +++ b/pdk/open_road_configuration.bzl @@ -31,6 +31,7 @@ OpenRoadPdkInfo = provider( "do_not_use_cell_list": "Do not use cells in timing repair. This supports wild card * cell names", "cts_buffer_cell": "Clock Tree Buffer cell", "fill_cells": "Metal fill cells", + "ha_fa_mapping": "HA/FA techmapping file", "global_routing_layer_adjustments": "Global routing adjustment layers", "global_routing_clock_layers": "Clock routing layers", "global_routing_signal_layers": "Signal routing layers", @@ -69,6 +70,7 @@ def _open_road_pdk_configuration_impl(ctx): do_not_use_cell_list = ctx.attr.do_not_use_cell_list, cts_buffer_cell = ctx.attr.cts_buffer_cell, fill_cells = ctx.attr.fill_cells, + ha_fa_mapping = ctx.attr.ha_fa_mapping, global_routing_layer_adjustments = ctx.attr.global_routing_layer_adjustments, global_routing_clock_layers = ctx.attr.global_routing_clock_layers, global_routing_signal_layers = ctx.attr.global_routing_signal_layers, @@ -102,6 +104,7 @@ open_road_pdk_configuration = rule( "do_not_use_cell_list": attr.string_list(mandatory = True, doc = "This value can be an empty list if all cells should be used in P&R"), "cts_buffer_cell": attr.string(mandatory = True, doc = "Clock Tree Buffer cell"), "fill_cells": attr.string_list(mandatory = True), + "ha_fa_mapping": attr.label(allow_single_file = True, doc = "Yosys specific HA/FA techmapping file"), "global_routing_layer_adjustments": attr.string_dict(mandatory = True), "global_routing_clock_layers": attr.string(mandatory = True), "global_routing_signal_layers": attr.string(mandatory = True), diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index ef5cea72..6201978b 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -136,6 +136,12 @@ def _synthesize_design_impl(ctx): if or_config.tie_high_port: script_env_files["TIEHI_CELL_AND_PORT"] = str(or_config.tie_high_port) + ha_fa_mapping = or_config.ha_fa_mapping + if ha_fa_mapping: + ha_fa_mapping_path = ha_fa_mapping.files.to_list()[0].path + script_env_files["ADDER_MAPPING"] = str(ha_fa_mapping_path) + inputs.append(ha_fa_mapping.files.to_list()[0]) + env = { "YOSYS_DATDIR": yosys_runfiles_dir + "/at_clifford_yosys/techlibs/", "ABC": yosys_runfiles_dir + "/edu_berkeley_abc/abc", @@ -259,6 +265,10 @@ synthesize_rtl = rule( allow_single_file = True, doc = "Tcl synthesis script compatible with the environment-variable API of synth.tcl", ), + "adder_mapping": attr.label( + allow_single_file = True, + doc = "Verilog file that maps yosys adder to PDK adders." + ), "target_clock_period_pico_seconds": attr.int(doc = "target clock period in picoseconds"), "output_file_name": attr.string(doc = "The output file name."), }, diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl index 3ba20aec..2821e330 100644 --- a/synthesis/synth.tcl +++ b/synthesis/synth.tcl @@ -72,10 +72,23 @@ yosys synth -top $top yosys opt_clean -purge yosys autoname +# Technology mapping of adders +if {[info exists ::env(ADDER_MAPPING)] && [file isfile $::env(ADDER_MAPPING)]} { + # extract the full adders + extract_fa + # map full adders + techmap -map $::env(ADDER_MAPPING) + techmap + # Quick optimization + opt -fast -purge +} + # mapping to liberty set liberty $::env(LIBERTY) dfflibmap -liberty $liberty +opt + if { [info exists ::env(CLOCK_PERIOD) ] } { abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD) {*}$::env(DONT_USE_ARGS) } else {