From 841ee27234664a98298a569390e7ea09e5878abc Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 31 Dec 2023 12:47:15 -0800 Subject: [PATCH] Temp. --- benchmarks/BUILD | 0 benchmarks/basic/BUILD | 15 ++ benchmarks/basic/add/BUILD | 202 +++++++++++++++++++++ benchmarks/basic/add/asap7.sdc | 1 + benchmarks/basic/add/mod_add.sv | 8 + benchmarks/basic/add/sky130.sdc | 6 + benchmarks/basic/add/top_add.sv | 36 ++++ benchmarks/basic/and/BUILD | 202 +++++++++++++++++++++ benchmarks/basic/and/mod_and.sv | 8 + benchmarks/basic/and/top_and.sv | 36 ++++ benchmarks/basic/common/asap7.sdc | 6 + benchmarks/basic/common/place.diagonal.tcl | 64 +++++++ benchmarks/basic/common/place.loopback.tcl | 64 +++++++ benchmarks/basic/common/place.straight.tcl | 62 +++++++ benchmarks/basic/common/sky130.sdc | 6 + benchmarks/basic/genbuild.py | 172 ++++++++++++++++++ benchmarks/basic/mul/BUILD | 202 +++++++++++++++++++++ benchmarks/basic/mul/mod_mul.sv | 8 + benchmarks/basic/mul/top_mul.sv | 36 ++++ benchmarks/basic/xand/BUILD | 202 +++++++++++++++++++++ benchmarks/basic/xand/mod_xand.sv | 15 ++ benchmarks/basic/xand/top_xand.sv | 36 ++++ 22 files changed, 1387 insertions(+) create mode 100644 benchmarks/BUILD create mode 100644 benchmarks/basic/BUILD create mode 100644 benchmarks/basic/add/BUILD create mode 100644 benchmarks/basic/add/asap7.sdc create mode 100644 benchmarks/basic/add/mod_add.sv create mode 100644 benchmarks/basic/add/sky130.sdc create mode 100644 benchmarks/basic/add/top_add.sv create mode 100644 benchmarks/basic/and/BUILD create mode 100644 benchmarks/basic/and/mod_and.sv create mode 100644 benchmarks/basic/and/top_and.sv create mode 100644 benchmarks/basic/common/asap7.sdc create mode 100644 benchmarks/basic/common/place.diagonal.tcl create mode 100644 benchmarks/basic/common/place.loopback.tcl create mode 100644 benchmarks/basic/common/place.straight.tcl create mode 100644 benchmarks/basic/common/sky130.sdc create mode 100755 benchmarks/basic/genbuild.py create mode 100644 benchmarks/basic/mul/BUILD create mode 100644 benchmarks/basic/mul/mod_mul.sv create mode 100644 benchmarks/basic/mul/top_mul.sv create mode 100644 benchmarks/basic/xand/BUILD create mode 100644 benchmarks/basic/xand/mod_xand.sv create mode 100644 benchmarks/basic/xand/top_xand.sv diff --git a/benchmarks/BUILD b/benchmarks/BUILD new file mode 100644 index 00000000..e69de29b diff --git a/benchmarks/basic/BUILD b/benchmarks/basic/BUILD new file mode 100644 index 00000000..cb846aca --- /dev/null +++ b/benchmarks/basic/BUILD @@ -0,0 +1,15 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +exports_files(glob(["common/**"])) diff --git a/benchmarks/basic/add/BUILD b/benchmarks/basic/add/BUILD new file mode 100644 index 00000000..22beb7ae --- /dev/null +++ b/benchmarks/basic/add/BUILD @@ -0,0 +1,202 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for add """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +verilog_library( + name = "rtl", + srcs = [ + "top_add.sv", + "mod_add.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for add on asap7 with sc7p5t_rev27 +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for add on asap7 with sc7p5t_rev27 using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for add on asap7 with sc7p5t_rev27 using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for add on asap7 with sc7p5t_rev27 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for add on sky130 with sc_hd +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for add on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for add on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for add on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/add/asap7.sdc b/benchmarks/basic/add/asap7.sdc new file mode 100644 index 00000000..cabef46b --- /dev/null +++ b/benchmarks/basic/add/asap7.sdc @@ -0,0 +1 @@ +set clk_port_name "clk" \ No newline at end of file diff --git a/benchmarks/basic/add/mod_add.sv b/benchmarks/basic/add/mod_add.sv new file mode 100644 index 00000000..802e358b --- /dev/null +++ b/benchmarks/basic/add/mod_add.sv @@ -0,0 +1,8 @@ +module mod_add( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x = a + b; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/add/sky130.sdc b/benchmarks/basic/add/sky130.sdc new file mode 100644 index 00000000..3f5d1d0d --- /dev/null +++ b/benchmarks/basic/add/sky130.sdc @@ -0,0 +1,6 @@ +set clk_port_name "clk" +set clk_period 10 +set clk_half_period [format "%.5f" [expr {$clk_period / 2.0}]] + +create_clock -name clk -period $clk_period -waveform "0 $clk_half_period" \ + [get_ports -quiet $clk_port_name] \ No newline at end of file diff --git a/benchmarks/basic/add/top_add.sv b/benchmarks/basic/add/top_add.sv new file mode 100644 index 00000000..88947822 --- /dev/null +++ b/benchmarks/basic/add/top_add.sv @@ -0,0 +1,36 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +module top_add ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_add mod (.a(a_), .b(b_), .x(i_)); + +endmodule diff --git a/benchmarks/basic/and/BUILD b/benchmarks/basic/and/BUILD new file mode 100644 index 00000000..2e153af1 --- /dev/null +++ b/benchmarks/basic/and/BUILD @@ -0,0 +1,202 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for and """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +verilog_library( + name = "rtl", + srcs = [ + "top_and.sv", + "mod_and.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for and on asap7 with sc7p5t_rev27 +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for and on asap7 with sc7p5t_rev27 using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for and on asap7 with sc7p5t_rev27 using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for and on asap7 with sc7p5t_rev27 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for and on sky130 with sc_hd +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for and on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for and on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for and on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/and/mod_and.sv b/benchmarks/basic/and/mod_and.sv new file mode 100644 index 00000000..daf5ac82 --- /dev/null +++ b/benchmarks/basic/and/mod_and.sv @@ -0,0 +1,8 @@ +module mod_and( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x = a & b; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/and/top_and.sv b/benchmarks/basic/and/top_and.sv new file mode 100644 index 00000000..61238f21 --- /dev/null +++ b/benchmarks/basic/and/top_and.sv @@ -0,0 +1,36 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +module top_and ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_and mod (.a(a_), .b(b_), .x(i_)); + +endmodule diff --git a/benchmarks/basic/common/asap7.sdc b/benchmarks/basic/common/asap7.sdc new file mode 100644 index 00000000..3f5d1d0d --- /dev/null +++ b/benchmarks/basic/common/asap7.sdc @@ -0,0 +1,6 @@ +set clk_port_name "clk" +set clk_period 10 +set clk_half_period [format "%.5f" [expr {$clk_period / 2.0}]] + +create_clock -name clk -period $clk_period -waveform "0 $clk_half_period" \ + [get_ports -quiet $clk_port_name] \ No newline at end of file diff --git a/benchmarks/basic/common/place.diagonal.tcl b/benchmarks/basic/common/place.diagonal.tcl new file mode 100644 index 00000000..712452c9 --- /dev/null +++ b/benchmarks/basic/common/place.diagonal.tcl @@ -0,0 +1,64 @@ +set db [ord::get_db_block] + +set core_area [$db getCoreArea] +set core_area_x0 [$core_area xMin] +set core_area_x1 [$core_area xMax] +set core_area_width [expr {$core_area_x1 - $core_area_x0}] + +set core_area_y0 [$core_area yMin] +set core_area_y1 [$core_area yMax] +set core_area_height [expr {$core_area_y1 - $core_area_y0}] + +puts "\nCoreArea (($core_area_x0,$core_area_y0) ($core_area_x1,$core_area_y1)) ($core_area_width x $core_area_height)\n" + +set dff0 [$db findInst "mod.a0_\$_DFF_P__Q"] +set dff0_bbox [$dff0 getBBox] +set dff0_width [$dff0_bbox getDX] +set dff0_height [$dff0_bbox getDY] + +puts "\nDFF size is $dff0_width x $dff0_height\n" + +puts "\nUsing diagonal placement" +puts " * Inputs A on left edge" +puts " * Inputs B on top edge" +puts " * Outputs X on right edge" + +set pad 0 + +set y0 [expr {$core_area_y0 + $pad}] +set x0 [expr {$core_area_x0 + $pad}] +set xn [expr {$core_area_x1 - $dff0_width - $pad}] + +set flops 8 + +set y_group_size [expr {$core_area_height / ($flops + 2)}] +set x_group_size [expr {$core_area_width / ($flops + 2)}] + +set y [expr {$y0 + $y_group_size / 2 + $y_group_size}] +set x [expr {$x0 + $x_group_size / 2 + $x_group_size}] + +for {set i 0} {$i < $flops} {incr i} { + set a_dff_name "mod.a$i\_\$_DFF_P__Q" + set a_dff [$db findInst $a_dff_name] + $a_dff setLocation $x0 $y + $a_dff setPlacementStatus "PLACED" + puts "Placed on left edge $a_dff_name @ ($x0 $y)" + + set x_dff_name "x$i\_\$_DFF_P__Q" + set x_dff [$db findInst $x_dff_name] + $x_dff setLocation $xn $y + $x_dff setPlacementStatus "PLACED" + puts "Placed on right $x_dff_name @ ($xn $y)" + + set y [expr {$y + $y_group_size}] + + set b_dff_name "mod.b$i\_\$_DFF_P__Q" + set b_dff [$db findInst $b_dff_name] + $b_dff setLocation $x $y0 + $b_dff setPlacementStatus "PLACED" + puts "Placed on top edge $b_dff_name @ ($x $y0)" + + set x [expr {$x + $x_group_size}] + + puts "" +} diff --git a/benchmarks/basic/common/place.loopback.tcl b/benchmarks/basic/common/place.loopback.tcl new file mode 100644 index 00000000..bd3b553f --- /dev/null +++ b/benchmarks/basic/common/place.loopback.tcl @@ -0,0 +1,64 @@ +set db [ord::get_db_block] + +set core_area [$db getCoreArea] +set core_area_x0 [$core_area xMin] +set core_area_x1 [$core_area xMax] +set core_area_width [expr {$core_area_x1 - $core_area_x0}] + +set core_area_y0 [$core_area yMin] +set core_area_y1 [$core_area yMax] +set core_area_height [expr {$core_area_y1 - $core_area_y0}] + +puts "\nCoreArea (($core_area_x0,$core_area_y0) ($core_area_x1,$core_area_y1)) ($core_area_width x $core_area_height)\n" + +set dff0 [$db findInst "mod.a0_\$_DFF_P__Q"] +set dff0_bbox [$dff0 getBBox] +set dff0_width [$dff0_bbox getDX] +set dff0_height [$dff0_bbox getDY] + +puts "\nDFF size is $dff0_width x $dff0_height\n" + +puts "\nUsing loopback placement" +puts " * Inputs A on left edge" +puts " * Inputs B on left edge" +puts " * Outputs X on left edge" + +set pad 0 + +set y0 [expr {$core_area_y0 + $pad}] + +set x0 [expr {$core_area_x0 + $pad}] +set xn [expr {$core_area_x1 - $dff0_width - $pad}] + +set flops 8 + +set y_ff_offset [expr {$dff0_height * 2}] +set y_group_size [expr {$core_area_height / ($flops + 2)}] + +set y [expr {$y0 + $y_group_size / 2 + $y_group_size}] + +for {set i 0} {$i < $flops} {incr i} { + set a_dff_name "mod.a$i\_\$_DFF_P__Q" + set a_dff [$db findInst $a_dff_name] + set y_a $y + $a_dff setLocation $x0 $y_a + $a_dff setPlacementStatus "PLACED" + puts "Placed on left edge $a_dff_name @ ($x0 $y_a)" + + set b_dff_name "mod.b$i\_\$_DFF_P__Q" + set b_dff [$db findInst $b_dff_name] + set y_b [expr {$y + $y_ff_offset}] + $b_dff setLocation $x0 $y_b + $b_dff setPlacementStatus "PLACED" + puts "Placed on left edge $b_dff_name @ ($x0 $y_b)" + + set x_dff_name "x$i\_\$_DFF_P__Q" + set x_dff [$db findInst $x_dff_name] + set y_x [expr {$y + $y_ff_offset * 2}] + $x_dff setLocation $x0 $y_x + $x_dff setPlacementStatus "PLACED" + puts "Placed on left edge $x_dff_name @ ($x0 $y_x)" + + set y [expr {$y + $y_group_size}] + puts "" +} diff --git a/benchmarks/basic/common/place.straight.tcl b/benchmarks/basic/common/place.straight.tcl new file mode 100644 index 00000000..80bf4341 --- /dev/null +++ b/benchmarks/basic/common/place.straight.tcl @@ -0,0 +1,62 @@ +set db [ord::get_db_block] + +set core_area [$db getCoreArea] +set core_area_x0 [$core_area xMin] +set core_area_x1 [$core_area xMax] +set core_area_width [expr {$core_area_x1 - $core_area_x0}] + +set core_area_y0 [$core_area yMin] +set core_area_y1 [$core_area yMax] +set core_area_height [expr {$core_area_y1 - $core_area_y0}] + +puts "\nCoreArea (($core_area_x0,$core_area_y0) ($core_area_x1,$core_area_y1)) ($core_area_width x $core_area_height)\n" + +set dff0 [$db findInst "mod.a0_\$_DFF_P__Q"] +set dff0_bbox [$dff0 getBBox] +set dff0_width [$dff0_bbox getDX] +set dff0_height [$dff0_bbox getDY] + +puts "\nDFF size is $dff0_width x $dff0_height\n" + +puts "\nUsing 'straight' placement" +puts " * Inputs A on left edge" +puts " * Inputs B on left edge" +puts " * Outputs X on right edge" + +set pad 0 + +set y0 [expr {$core_area_y0 + $pad}] + +set x0 [expr {$core_area_x0 + $pad}] +set xn [expr {$core_area_x1 - $dff0_width - $pad}] + +set flops 8 + +set y_ff_offset [expr {$dff0_height * 2}] +set y_group_size [expr {$core_area_height / ($flops + 2)}] + +set y [expr {$y0 + $y_group_size / 2 + $y_group_size}] + +for {set i 0} {$i < $flops} {incr i} { + set a_dff_name "mod.a$i\_\$_DFF_P__Q" + set a_dff [$db findInst $a_dff_name] + $a_dff setLocation $x0 $y + $a_dff setPlacementStatus "PLACED" + puts "Placed $a_dff_name @ ($x0 $y)" + + set b_dff_name "mod.b$i\_\$_DFF_P__Q" + set b_dff [$db findInst $b_dff_name] + set y_b [expr {$y + $y_ff_offset}] + $b_dff setLocation $x0 $y_b + $b_dff setPlacementStatus "PLACED" + puts "Placed $b_dff_name @ ($x0 $y_b)" + + set x_dff_name "x$i\_\$_DFF_P__Q" + set x_dff [$db findInst $x_dff_name] + $x_dff setLocation $xn $y + $x_dff setPlacementStatus "PLACED" + puts "Placed $x_dff_name @ ($xn $y)" + + set y [expr {$y + $y_group_size}] + puts "" +} diff --git a/benchmarks/basic/common/sky130.sdc b/benchmarks/basic/common/sky130.sdc new file mode 100644 index 00000000..3f5d1d0d --- /dev/null +++ b/benchmarks/basic/common/sky130.sdc @@ -0,0 +1,6 @@ +set clk_port_name "clk" +set clk_period 10 +set clk_half_period [format "%.5f" [expr {$clk_period / 2.0}]] + +create_clock -name clk -period $clk_period -waveform "0 $clk_half_period" \ + [get_ports -quiet $clk_port_name] \ No newline at end of file diff --git a/benchmarks/basic/genbuild.py b/benchmarks/basic/genbuild.py new file mode 100755 index 00000000..0c910621 --- /dev/null +++ b/benchmarks/basic/genbuild.py @@ -0,0 +1,172 @@ +#!/usr/bin/env python3 +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +import pathlib +import subprocess + +LICENSE = [] +with open(__file__) as f: + while True: + l = next(f) + if not l.startswith("#!"): + break + while l.startswith('#'): + LICENSE.append(l[1:]) + l = next(f) + +PDKS = { + "asap7": { + "libraries": ["sc7p5t_rev27"], + "pnr": { + "core_padding_microns": 2, + "die_height_microns": 400, + "die_width_microns": 400, + "skip_detailed_routing": False, + } + }, + "sky130": { + "libraries": ['sc_hd'], + "pnr": { + "core_padding_microns": 2, + "die_height_microns": 200, + "die_width_microns": 100, + "skip_detailed_routing": False, + } + }, +} + +FILE_DIR = pathlib.Path(__file__).parent + +MODULES = [ + "and", + "xand", + "add", + "mul", +] + +PLACEMENT = [ + "straight", + "loopback", + "diagonal", +] + +for MOD_NAME in MODULES: + with open(FILE_DIR / MOD_NAME / f"top_{MOD_NAME}.sv", "w", encoding="utf-8") as top_file: + top_file.write(''.join('//'+l for l in LICENSE)) + top_file.write(f"""\ +module top_{MOD_NAME} ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_{MOD_NAME} mod (.a(a_), .b(b_), .x(i_)); + +endmodule +""") + + build_file_name = FILE_DIR / MOD_NAME / f"BUILD" + print("Writing ", build_file_name, "...") + with open(build_file_name, "w", encoding="utf-8") as build_file: + build_file.write(''.join('#'+l for l in LICENSE)) + build_file.write(f''' +""" Benchmark for {MOD_NAME} """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +verilog_library( + name = "rtl", + srcs = [ + "top_{MOD_NAME}.sv", + "mod_{MOD_NAME}.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) +''') + + for PDK_NAME, PDK_CONFIG in PDKS.items(): + for LIB in PDK_CONFIG['libraries']: + build_file.write(f""" +# Run for {MOD_NAME} on {PDK_NAME} with {LIB} +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/{PDK_NAME}.sdc", + skip_detailed_routing = {PDK_CONFIG['pnr']['skip_detailed_routing']}, + core_padding_microns = {PDK_CONFIG['pnr']['core_padding_microns']}, + die_height_microns = {PDK_CONFIG['pnr']['die_height_microns']}, + die_width_microns = {PDK_CONFIG['pnr']['die_width_microns']}, + ), + ), + target = ":rtl", + top = "top_{MOD_NAME}", + ) + for cell_name, cell_target in for_each_{PDK_NAME}_cells("{LIB}") +] +""") + + for PLACE in PLACEMENT: + build_file.write(f""" +# Run for {MOD_NAME} on {PDK_NAME} with {LIB} using {PLACE} placement. +[ + basic_asic_flow( + name = "{PLACE}-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/{PDK_NAME}.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.{PLACE}.tcl", + skip_detailed_routing = {PDK_CONFIG['pnr']['skip_detailed_routing']}, + core_padding_microns = {PDK_CONFIG['pnr']['core_padding_microns']}, + die_height_microns = {PDK_CONFIG['pnr']['die_height_microns']}, + die_width_microns = {PDK_CONFIG['pnr']['die_width_microns']}, + ), + ), + target = ":rtl", + top = "top_{MOD_NAME}", + ) + for cell_name, cell_target in for_each_{PDK_NAME}_cells("{LIB}") +] +""") + +# subprocess.check_call(f"buildifier {build_file}", shell=True) diff --git a/benchmarks/basic/mul/BUILD b/benchmarks/basic/mul/BUILD new file mode 100644 index 00000000..553c49bd --- /dev/null +++ b/benchmarks/basic/mul/BUILD @@ -0,0 +1,202 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for mul """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +verilog_library( + name = "rtl", + srcs = [ + "top_mul.sv", + "mod_mul.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for mul on asap7 with sc7p5t_rev27 +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for mul on asap7 with sc7p5t_rev27 using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for mul on asap7 with sc7p5t_rev27 using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for mul on asap7 with sc7p5t_rev27 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for mul on sky130 with sc_hd +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for mul on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for mul on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for mul on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/mul/mod_mul.sv b/benchmarks/basic/mul/mod_mul.sv new file mode 100644 index 00000000..636522ac --- /dev/null +++ b/benchmarks/basic/mul/mod_mul.sv @@ -0,0 +1,8 @@ +module mod_mul( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x = a * b; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/mul/top_mul.sv b/benchmarks/basic/mul/top_mul.sv new file mode 100644 index 00000000..52485313 --- /dev/null +++ b/benchmarks/basic/mul/top_mul.sv @@ -0,0 +1,36 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +module top_mul ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_mul mod (.a(a_), .b(b_), .x(i_)); + +endmodule diff --git a/benchmarks/basic/xand/BUILD b/benchmarks/basic/xand/BUILD new file mode 100644 index 00000000..1970c5d7 --- /dev/null +++ b/benchmarks/basic/xand/BUILD @@ -0,0 +1,202 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for xand """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +verilog_library( + name = "rtl", + srcs = [ + "top_xand.sv", + "mod_xand.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for xand on asap7 with sc7p5t_rev27 +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for xand on asap7 with sc7p5t_rev27 using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for xand on asap7 with sc7p5t_rev27 using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for xand on asap7 with sc7p5t_rev27 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") +] + +# Run for xand on sky130 with sc_hd +[ + basic_asic_flow( + name = cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for xand on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for xand on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for xand on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-"+cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + skip_detailed_routing = False, + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/xand/mod_xand.sv b/benchmarks/basic/xand/mod_xand.sv new file mode 100644 index 00000000..ca690a1d --- /dev/null +++ b/benchmarks/basic/xand/mod_xand.sv @@ -0,0 +1,15 @@ +module mod_xand( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x[0] = a[0] & b[0]; + assign x[1] = x[0] & a[1] & b[1]; + assign x[2] = x[1] & a[2] & b[2]; + assign x[3] = x[2] & a[3] & b[3]; + assign x[4] = x[3] & a[4] & b[4]; + assign x[5] = x[4] & a[5] & b[5]; + assign x[6] = x[5] & a[6] & b[6]; + assign x[7] = x[6] & a[7] & b[7]; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/xand/top_xand.sv b/benchmarks/basic/xand/top_xand.sv new file mode 100644 index 00000000..4b1ff6ee --- /dev/null +++ b/benchmarks/basic/xand/top_xand.sv @@ -0,0 +1,36 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +module top_xand ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_xand mod (.a(a_), .b(b_), .x(i_)); + +endmodule