Adding support for synth.tcl to read SystemVerilog files using Sure…

…log. Signed-off-by: Tim Ansell <[email protected]>
mithro · Sep 18, 2023 · 9d15bef · 9d15bef
1 parent 3ba0ef0
commit 9d15bef
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
@@ -21,7 +21,11 @@ foreach src $srcs {
     # Skip empty lines, including the implict one after the last \n delimiter
     # for files that end with a newline.
     if {$src eq ""} continue
-    yosys read_verilog -sv -defer $src
+    if {[info exists ::env(USE_SURELOG_FRONTEND)]} {
+      yosys read_systemverilog $src
+    } else {
+      yosys read_verilog -sv -defer $src
+    }
 }
 
 # read UHDM designs