diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl
index 14b1b460..383acae4 100644
--- a/synthesis/build_defs.bzl
+++ b/synthesis/build_defs.bzl
@@ -112,12 +112,19 @@ def _synthesize_design_impl(ctx):
     args.add_all("-l", [log_file])  # put output in log file
     args.add_all("-c", [synth_tcl])  # run synthesis tcl script
 
+    dont_use_args = ""
+    or_config = ctx.attr.standard_cells[StandardCellInfo].open_road_configuration
+    if or_config:
+        for dont_use_pattern in or_config.do_not_use_cell_list:
+            dont_use_args += " -dont_use {} ".format(dont_use_pattern)
+
     script_env_files = {
         "FLIST": verilog_flist,
         "UHDM_FLIST": uhdm_flist,
         "TOP": ctx.attr.top_module,
         "OUTPUT": output_file,
         "LIBERTY": default_liberty_file,
+        "DONT_USE_ARGS": dont_use_args,
     }
 
     if ctx.attr.target_clock_period_pico_seconds:
diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
index 0e2b1237..709a8d34 100644
--- a/synthesis/synth.tcl
+++ b/synthesis/synth.tcl
@@ -53,9 +53,9 @@ set liberty $::env(LIBERTY)
 dfflibmap -liberty $liberty
 
 if { [info exists ::env(CLOCK_PERIOD) ] } {
-  abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD)
+  abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD) {*}$::env(DONT_USE_ARGS)
 } else {
-  abc -liberty $liberty -dff -g aig
+  abc -liberty $liberty -dff -g aig {*}$::env(DONT_USE_ARGS)
 }
 
 # write synthesized design