From b47d59d948de4505c41b8fbb2158105540fb3b25 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 20 Dec 2023 15:00:01 +1030 Subject: [PATCH] Refactor tests. * Test each step by itself. * Create a `basic_asic_flow` and use it to test each configured standard cell libraries for both supported PDKs (`SKY130` & `ASAP7`). * Remove the `asap7.bzl` as the `for_each_XXX_cells` macro and `basic_asic_flow` are a better replacement. * Rename `counter.v` to `verilog_counter.v` to be consistent with `verilog_adder.v`. Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Tim Ansell --- flows/asap7.bzl | 104 --------- flows/basic_asic.bzl | 130 +++++++++++ pdk/build_defs.bzl | 44 +++- place_and_route/build_defs.bzl | 2 +- place_and_route/private/detailed_routing.bzl | 2 +- synthesis/tests/BUILD | 183 ---------------- tests/BUILD | 203 ++++++++++++++++++ {synthesis/tests => tests}/constraint.sdc | 0 {synthesis/tests => tests}/verilog_adder.v | 2 +- .../counter.v => tests/verilog_counter.v | 2 +- 10 files changed, 376 insertions(+), 296 deletions(-) delete mode 100644 flows/asap7.bzl create mode 100644 flows/basic_asic.bzl delete mode 100644 synthesis/tests/BUILD create mode 100644 tests/BUILD rename {synthesis/tests => tests}/constraint.sdc (100%) rename {synthesis/tests => tests}/verilog_adder.v (97%) rename synthesis/tests/counter.v => tests/verilog_counter.v (97%) diff --git a/flows/asap7.bzl b/flows/asap7.bzl deleted file mode 100644 index 258b998a..00000000 --- a/flows/asap7.bzl +++ /dev/null @@ -1,104 +0,0 @@ -# Copyright 2021-2022 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" Macro for quick ASAP7 basic flow. """ - -load("@bazel_skylib//rules:build_test.bzl", "build_test") -load("//gds_write:build_defs.bzl", "gds_write") -load("//place_and_route:build_defs.bzl", "place_and_route") -load("//static_timing:build_defs.bzl", "run_opensta") -load("//synthesis:build_defs.bzl", "synthesize_rtl") - -def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20, corners = ("ccs_ss", "ccs_tt", "ccs_ff")): - """Generate targets for a quick basic ASAP7 flow. - - Args: - name: Name for the macro instance. - target: Verilog library name. - rev: ASAP7 revision (26 / 27 / 28). - tracks: Number of tracks ("7p5t", "6t"). - vt: VT type ("rvt", "lvt", "slvt"). - has_gds: Cells have GDS layouts. - size: Size of the die in microns. - corners: List of corners to generate rules for (default is `ccs_ss`, `ccs_tt`, `ccs_ff`). - """ - if rev not in [26, 27, 28]: - fail("Invalid rev {}".format(repr(rev))) - if tracks not in ["7p5t", "6t"]: - fail("Invalid rev {}".format(repr(tracks))) - - # TODO: Add the NLDM support once it works with OpenROAD. - for corner in corners: - a = { - "name": target, - "tracks": tracks, - "rev": rev, - "vt": vt, - "corn": corner, - } - - synthesize_rtl( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}-{corn}".format(**a), - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":{name}".format(**a), - ], - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ], - ) - - run_opensta( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a), - synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ], - ) - - place_and_route( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - core_padding_microns = 1, - die_height_microns = size, - die_width_microns = size, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - ], - ) - - if has_gds: - gds_write( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), - implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), - ], - ) diff --git a/flows/basic_asic.bzl b/flows/basic_asic.bzl new file mode 100644 index 00000000..594f7822 --- /dev/null +++ b/flows/basic_asic.bzl @@ -0,0 +1,130 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Very basic ASIC flow, mainly used for testing and debugging.""" + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("//gds_write:build_defs.bzl", "gds_write") +load("//place_and_route:build_defs.bzl", "place_and_route") +load("//static_timing:build_defs.bzl", "run_opensta") +load("//synthesis:build_defs.bzl", "synthesize_rtl") + +def _get_with_defaults(target_name, extra_args, defaults): + target_extra_args = extra_args.pop(target_name, {}) + for k, v in defaults.items(): + if k not in target_extra_args: + target_extra_args[k] = v + return target_extra_args + +def basic_asic_flow(name, target, cells, top = None, extra_args = {}, gds = True, size = 20): + """Generate targets for a basic ASIC flow. + + Args: + name: Name for the macro instance. + target: Verilog library name. + cells: Standard cells to use. + top: Name of the top level module (defaults to name). + gds: Run all the way to GDS output. + extra_args: Extra arguments to provide the steps in the flow. + size: Size of the die in microns. + """ + if top == None: + top = name + extra_args = dict(**extra_args) + + # Synthesis + synthesize_rtl( + name = name + "-step1-synth", + standard_cells = cells, + top_module = top, + deps = [ + target, + ], + **_get_with_defaults( + "synthesize_rtl", + extra_args, + dict( + target_clock_period_pico_seconds = 10000, + ), + ) + ) + build_test( + name = "build-" + name + "-step1-synth", + targets = [":" + name + "-step1-synth"], + ) + + # Static timing analysis of synthesis result + run_opensta( + name = name + "-step1-synth_sta", + synth_target = ":" + name + "-step1-synth", + **_get_with_defaults( + "synth_run_opensta", + extra_args, + dict( + # No defaults at the moment. + ), + ) + ) + build_test( + name = "build-" + name + "-step1-synth_sta", + targets = [":" + name + "-step1-synth_sta"], + ) + + # Place and Route + place_and_route( + name = name + "-step2-place_and_route", + synthesized_rtl = ":" + name + "-step1-synth", + **_get_with_defaults( + "place_and_route", + extra_args, + dict( + placement_density = "0.65", + core_padding_microns = 1, + die_height_microns = size, + die_width_microns = size, + ), + ) + ) + build_test( + name = "build-" + name + "-step2-place_and_route", + targets = [ + ":" + name + "-step2-place_and_route", + ], + ) + + # FIXME: Should add a post place and route run_opensta? + + # GDS Generation + if gds: + gds_write( + name = name + "-step3-gds", + implemented_rtl = ":" + name + "-step2-place_and_route", + **_get_with_defaults( + "gds_write", + extra_args, + dict( + # No defaults at the moment. + ), + ) + ) + build_test( + name = "build-" + name + "-step3-gds", + targets = [ + ":" + name + "-step3-gds", + ], + ) + + # Make sure everything in the extra_args dictionary has been used. + if extra_args: + fail("{} provided in 'extra_args' was not used, please remove.".format("and ".join(extra_args.keys()))) diff --git a/pdk/build_defs.bzl b/pdk/build_defs.bzl index a5fcb388..3a6fcbf4 100644 --- a/pdk/build_defs.bzl +++ b/pdk/build_defs.bzl @@ -12,8 +12,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""Providers for PDKs to be used by downstream synthesis. -""" +"""Providers for PDKs to be used by downstream synthesis.""" StandardCellInfo = provider( "Contains information about the standard cells used for synthesis", @@ -53,6 +52,12 @@ StandardCellOptionsInfo = provider( def temp_format(i): """Format an integer representing degrees celsius. + Args: + i: Temperature as integer in degrees celsius. + + Returns: + A formated string version of input. + The format is: * Always 4 characters long. * Always ends in lower case 'c'. @@ -90,7 +95,13 @@ def temp_format(i): return s + "c" def temp_parse(s): - """Parse into an int a string representing temperature in degrees celsius. + """Parse a string representing temperature in degrees celsius into integer. + + Args: + s: Temperature as string. + + Returns: + An integer representing temperature in degrees celsius. >>> temp_parse("030c") 30 @@ -116,7 +127,7 @@ def temp_parse(s): # Check string ends in `c` (for degree celsius) if s[-1] != "c": - fail("No `c` character found at end of value {}".format(s)) + fail("No `c` character found at end of value {} (input {})".format(s, os)) s = s[:-1] # Convert `m` into negative sign @@ -137,6 +148,12 @@ def temp_parse(s): def temp_normalize(s): """Normalize an already existing temperature string into the format provided by `temp_format`. + Args: + s: Temperature as string. + + Returns: + A normalize version of the input string. + >>> temp_normalize("m2c") "m02c" @@ -154,6 +171,12 @@ def temp_normalize(s): def voltage_format(f): """Format a decimal number representing a voltage. + Args: + f: Voltage as decimal number (float / int). + + Returns: + A string version of the input. + The format is: * Always 5 characters long. * Has one digit before the decimal point. @@ -189,6 +212,12 @@ def voltage_format(f): def voltage_normalize(s): """Normalize an existing voltage string into the format provided by `voltage_format`. + Args: + s: Voltage as string. + + Returns: + A normalize version of the input string. + >>> voltage_normalize("7p5v") "7v500" @@ -197,13 +226,18 @@ def voltage_normalize(s): >>> voltage_normalize("7.5v") "7v500" - """ return voltage_format(voltage_parse(s)) def voltage_parse(s): """Parse a voltage string like that produced by `voltage_format` function. + Args: + s: Voltage as string. + + Returns: + A float version of the input string. + >>> voltage_parse("7p5") 7.5 diff --git a/place_and_route/build_defs.bzl b/place_and_route/build_defs.bzl index d6412dec..b749e194 100644 --- a/place_and_route/build_defs.bzl +++ b/place_and_route/build_defs.bzl @@ -105,6 +105,6 @@ place_and_route = rule( "sink_clustering_size": attr.int(doc = "Clock tree synthesis sink group size"), "sink_clustering_max_diameter": attr.int(doc = "Clock tree synthesis sink group desired diamater in microns"), "min_pin_distance": attr.string(doc = "The minimum distance in microns between pins around the outside of the block."), - "enable_improve_placement": attr.bool(default=True, doc = "Enable/Disable improve_placement pass.") + "enable_improve_placement": attr.bool(default = True, doc = "Enable/Disable improve_placement pass."), }, ) diff --git a/place_and_route/private/detailed_routing.bzl b/place_and_route/private/detailed_routing.bzl index b6f92fb3..fe1ca116 100644 --- a/place_and_route/private/detailed_routing.bzl +++ b/place_and_route/private/detailed_routing.bzl @@ -57,7 +57,7 @@ def detailed_routing(ctx, open_road_info): open_road_commands = timing_setup_command_struct.commands + [ "set_propagated_clock [all_clocks]", - "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args) + "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args), ] density_fill_config = None if open_road_configuration.density_fill_config: diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD deleted file mode 100644 index dc08b83d..00000000 --- a/synthesis/tests/BUILD +++ /dev/null @@ -1,183 +0,0 @@ -# Copyright 2021-2022 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -load("@bazel_skylib//rules:build_test.bzl", "build_test") -load("//flows:asap7.bzl", "asap7_targets") -load("//gds_write:build_defs.bzl", "gds_write") -load("//place_and_route:build_defs.bzl", "place_and_route") -load("//static_timing:build_defs.bzl", "run_opensta") -load("//synthesis:build_defs.bzl", "synthesize_rtl") -load("//verilog:providers.bzl", "verilog_library") - -package( - default_applicable_licenses = ["//:package_license"], - default_visibility = ["//visibility:private"], -) - -synthesize_rtl( - name = "verilog_adder_synthesized", - top_module = "adder", - deps = [ - ":verilog_adder", - ], -) - -verilog_library( - name = "verilog_adder", - srcs = [ - "verilog_adder.v", - ], -) - -########################################################################## -# Verilog counter -########################################################################## -verilog_library( - name = "verilog_counter", - srcs = [ - "counter.v", - ], -) - -# generic - -synthesize_rtl( - name = "verilog_counter-synth", - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-synth_sta", - synth_target = ":verilog_counter-synth", -) - -place_and_route( - name = "verilog_counter-place_and_route", - clock_period = "10", - core_padding_microns = 20, - die_height_microns = 200, - die_width_microns = 200, - placement_density = "0.7", - synthesized_rtl = ":verilog_counter-synth", -) - -gds_write( - name = "verilog_counter-gds", - implemented_rtl = ":verilog_counter-place_and_route", -) - -build_test( - name = "build-verilog_counter", - targets = [ - ":verilog_counter", - ":verilog_counter-synth", - ":verilog_counter-synth_sta", - ":verilog_counter-place_and_route", - ":verilog_counter-gds", - ], -) - -# ASAP7 7.5 track rev 28 -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev28_rvt", - rev = 28, - target = "verilog_counter", - tracks = "7p5t", - vt = "rvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev28_lvt", - rev = 28, - target = "verilog_counter", - tracks = "7p5t", - vt = "lvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev28_slvt", - rev = 28, - target = "verilog_counter", - tracks = "7p5t", - vt = "slvt", -) - -# ASAP7 7.5 track rev 27 -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt", - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "rvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_lvt", - has_gds = False, # No GDS for rev27 LVT - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "lvt", -) - -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_slvt", - has_gds = False, # No GDS for rev27 LVT - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "slvt", -) - -# ASAP7 7.5 track rev 27 4x scaled version -# FIXME: Enable the 4x scaled 7.5 track config. -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x", - size = 2000, - corners = ["ccs_ss"], - has_gds = False, # No GDS for the 4x cells - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "rvt_4x", -) - -# ASAP7 6 track rev 26 -# FIXME: Enable the 6 track config. -#asap7_targets( -# name = "verilog_counter-asap7-6t_rev26_rvt", -# rev = 26, -# target = "verilog_counter", -# tracks = "6t", -# vt = "rvt", -#) -# -#asap7_targets( -# name = "verilog_counter-asap7-6t_rev26_lvt", -# rev = 26, -# target = "verilog_counter", -# tracks = "6t", -# vt = "lvt", -#) -# -#asap7_targets( -# name = "verilog_counter-asap7-6t_rev26_slvt", -# rev = 26, -# target = "verilog_counter", -# tracks = "6t", -# vt = "slvt", -#) diff --git a/tests/BUILD b/tests/BUILD new file mode 100644 index 00000000..ab5156df --- /dev/null +++ b/tests/BUILD @@ -0,0 +1,203 @@ +# Copyright 2021-2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//gds_write:build_defs.bzl", "gds_write") +load("//place_and_route:build_defs.bzl", "place_and_route") +load("//static_timing:build_defs.bzl", "run_opensta") +load("//synthesis:build_defs.bzl", "synthesize_rtl") +load("//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +########################################################################## +# Basic tests of individual steps in the ASIC flow. +########################################################################## +BASIC_TESTS = [ + "verilog_adder", + "verilog_counter", +] + +# Basic `verilog_library` test +[ + verilog_library( + name = test_name, + srcs = [ + test_name + ".v", + ], + ) + for test_name in BASIC_TESTS +] + +# Basic `synthesize_rtl` test +[ + synthesize_rtl( + name = test_name + "-synth", + top_module = test_name, + deps = [ + ":" + test_name, + ], + ) + for test_name in BASIC_TESTS +] + +# Basic `run_opensta` test (on output of `synthesize_rtl`) +[ + run_opensta( + name = test_name + "-synth_sta", + synth_target = ":" + test_name + "-synth", + ) + for test_name in BASIC_TESTS +] + +# Basic `place_and_route` test (on output of `synthesize_rtl`) +place_and_route( + name = "verilog_adder-place_and_route", + clock_period = None, # Combinational only design + core_padding_microns = 20, + die_height_microns = 200, + die_width_microns = 200, + placement_density = "0.7", + synthesized_rtl = ":verilog_adder-synth", +) + +place_and_route( + name = "verilog_counter-place_and_route", + clock_period = "10", + core_padding_microns = 20, + die_height_microns = 200, + die_width_microns = 200, + placement_density = "0.7", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-synth", +) + +# Basic `gds_write` test (on output of `place_and_route`) +[ + gds_write( + name = test_name + "-gds", + implemented_rtl = ":" + test_name + "-place_and_route", + ) + for test_name in BASIC_TESTS +] + +# Make sure that all the basic tests above actually build +[ + build_test( + name = "build-" + test_name, + targets = [ + ":" + test_name, + ":" + test_name + "-synth", + ":" + test_name + "-synth_sta", + ":" + test_name + "-place_and_route", + ":" + test_name + "-gds", + ], + ) + for test_name in BASIC_TESTS +] + +########################################################################## +# Basic tests which run for each standard cell library. +########################################################################## + +EXTRA_ARGS = { + "verilog_counter": { + "place_and_route": dict( + sdc = "constraint.sdc", + ), + }, + "verilog_adder": { + "place_and_route": dict( + clock_period = None, # Combinational only design + ), + }, +} + +# SkyWater 130nm PDK +# ------------------------------------------------------------------------ +# Skywater 130nm PDK - High Density standard cells +[ + [ + basic_asic_flow( + name = test_name + "-" + cell_name, + size = 200, + cells = cell_target, + extra_args = EXTRA_ARGS[test_name], + target = ":" + test_name, + top = test_name, + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") + ] + for test_name in BASIC_TESTS +] + +# FIXME: Add other ('sc_hs', 'sc_ms', 'sc_ls', ...) +# Skywater 130nm PDK - XXXXX standard cells + +# ASAP7 predictive 7nm PDK +# ------------------------------------------------------------------------ + +# FIXME: Add ASAP7 7nm PDK - 6 track rev 26 standard cells + +# ASAP 7nm PDK - 7.5 track rev 27 standard cells +[ + [ + basic_asic_flow( + name = test_name + "-" + cell_name, + cells = cell_target, + extra_args = EXTRA_ARGS[test_name], + gds = False, # No GDS for the rev 27 cells + target = ":" + test_name, + top = test_name, + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev27") + ] + for test_name in BASIC_TESTS +] + +# ASAP 7nm PDK - 7.5 track rev 28 standard cells +[ + [ + basic_asic_flow( + name = test_name + "-" + cell_name, + size = 20, + cells = cell_target, + extra_args = EXTRA_ARGS[test_name], + target = ":" + test_name, + top = test_name, + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") + ] + for test_name in BASIC_TESTS +] + +# "Special" ASAP7 7.5 track rev 27 4x scaled version +[ + basic_asic_flow( + name = test_name + "-asap7-sc7p5t_rev27_rvt_4x", + size = 200, + cells = "@org_theopenroadproject_asap7sc7p5t_27//:asap7-sc7p5t_rev27_rvt_4x-ccs_ss", + extra_args = EXTRA_ARGS[test_name], + gds = False, # No GDS for the 4x cells + target = ":" + test_name, + top = test_name, + ) + for test_name in BASIC_TESTS +] diff --git a/synthesis/tests/constraint.sdc b/tests/constraint.sdc similarity index 100% rename from synthesis/tests/constraint.sdc rename to tests/constraint.sdc diff --git a/synthesis/tests/verilog_adder.v b/tests/verilog_adder.v similarity index 97% rename from synthesis/tests/verilog_adder.v rename to tests/verilog_adder.v index 3ca319e5..3e945b2e 100644 --- a/synthesis/tests/verilog_adder.v +++ b/tests/verilog_adder.v @@ -13,7 +13,7 @@ //limitations under the License. -module adder( +module verilog_adder( input [7:0] x, input [7:0] y, input carry_in, diff --git a/synthesis/tests/counter.v b/tests/verilog_counter.v similarity index 97% rename from synthesis/tests/counter.v rename to tests/verilog_counter.v index 33d671ed..c826eabb 100644 --- a/synthesis/tests/counter.v +++ b/tests/verilog_counter.v @@ -13,7 +13,7 @@ //limitations under the License. -module counter( +module verilog_counter( input wire clk, input wire reset, output [128:0] out,