diff --git a/dependency_support/org_theopenroadproject_asap7/asap7sc6t_rev26.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26.bzl similarity index 83% rename from dependency_support/org_theopenroadproject_asap7/asap7sc6t_rev26.bzl rename to dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26.bzl index bf02e6b9..75db2bfb 100644 --- a/dependency_support/org_theopenroadproject_asap7/asap7sc6t_rev26.bzl +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26.bzl @@ -19,26 +19,26 @@ # Standard cells filegroup( - name = "gds_cells_rvt", + name = "asap7-sc6t_rev26-gds_cells_rvt", srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_R.gds"], visibility = [":data_visibility"], ) filegroup( - name = "gds_cells_lvt", + name = "asap7-sc6t_rev26-gds_cells_lvt", srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_L.gds"], visibility = [":data_visibility"], ) filegroup( - name = "gds_cells_slvt", + name = "asap7-sc6t_rev26-gds_cells_slvt", srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_SL.gds"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "gds_sram", + name = "asap7-sc6t_rev26-gds_sram", srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_SRAM.gds"], visibility = [":data_visibility"], ) @@ -49,26 +49,26 @@ filegroup( # Standard cells filegroup( - name = "libgz_cells_rvt", + name = "asap7-sc6t_rev26-libgz_cells_rvt", srcs = glob(["asap7sc6t_26/LIB/CCS/*RVT*.lib.gz"]), visibility = [":data_visibility"], ) filegroup( - name = "libgz_cells_lvt", + name = "asap7-sc6t_rev26-libgz_cells_lvt", srcs = glob(["asap7sc6t_26/LIB/CCS/*LVT*.lib.gz"]), visibility = [":data_visibility"], ) filegroup( - name = "libgz_cells_slvt", + name = "asap7-sc6t_rev26-libgz_cells_slvt", srcs = glob(["asap7sc6t_26/LIB/CCS/*SLVT*.lib.gz"]), visibility = [":data_visibility"], ) # SRAM filegroup( - name = "libgz_sram", + name = "asap7-sc6t_rev26-libgz_sram", srcs = glob(["asap7sc6t_26/LIB/CCS/*SRAM*.lib.gz"]), visibility = [":data_visibility"], ) @@ -80,7 +80,7 @@ filegroup( # Standard cells filegroup( - name = "v_cells_rvt", + name = "asap7-sc6t_rev26-v_cells_rvt", srcs = [ "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_RVT_TT_210930.v", "asap7sc6t_26/Verilog/asap7sc7p5t_AO_RVT_TT_210930.v", @@ -93,7 +93,7 @@ filegroup( ) filegroup( - name = "v_cells_lvt", + name = "asap7-sc6t_rev26-v_cells_lvt", srcs = [ "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_LVT_TT_210930.v", "asap7sc6t_26/Verilog/asap7sc7p5t_AO_LVT_TT_210930.v", @@ -106,7 +106,7 @@ filegroup( ) filegroup( - name = "v_cells_slvt", + name = "asap7-sc6t_rev26-v_cells_slvt", srcs = [ "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_SLVT_TT_210930.v", "asap7sc6t_26/Verilog/asap7sc7p5t_AO_SLVT_TT_210930.v", @@ -120,7 +120,7 @@ filegroup( # SRAM filegroup( - name = "v_sram", + name = "asap7-sc6t_rev26-v_sram", srcs = [ "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_SRAM_TT_210930.v", "asap7sc6t_26/Verilog/asap7sc7p5t_AO_SRAM_TT_210930.v", @@ -137,26 +137,26 @@ filegroup( # Standard cells filegroup( - name = "lvs_cells_rvt", + name = "asap7-sc6t_rev26-lvs_cells_rvt", srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_R.cdl"], visibility = [":data_visibility"], ) filegroup( - name = "lvs_cells_lvt", + name = "asap7-sc6t_rev26-lvs_cells_lvt", srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_L.cdl"], visibility = [":data_visibility"], ) filegroup( - name = "lvs_cells_slvt", + name = "asap7-sc6t_rev26-lvs_cells_slvt", srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_SL.cdl"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lvs_sram", + name = "asap7-sc6t_rev26-lvs_sram", srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_SRAM.cdl"], visibility = [":data_visibility"], ) @@ -166,26 +166,26 @@ filegroup( # Standard cells filegroup( - name = "spice_cells_rvt", + name = "asap7-sc6t_rev26-spice_cells_rvt", srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_L_211010.sp"], visibility = [":data_visibility"], ) filegroup( - name = "spice_cells_lvt", + name = "asap7-sc6t_rev26-spice_cells_lvt", srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_R_211010.sp"], visibility = [":data_visibility"], ) filegroup( - name = "spice_cells_slvt", + name = "asap7-sc6t_rev26-spice_cells_slvt", srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_SL_211010.sp"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "spice_sram", + name = "asap7-sc6t_rev26-spice_sram", srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_SRAM_211010.sp"], visibility = [":data_visibility"], ) @@ -195,26 +195,26 @@ filegroup( # Standard cells filegroup( - name = "lef_cells_rvt", + name = "asap7-sc6t_rev26-lef_cells_rvt", srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_R_1x_210923b.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_lvt", + name = "asap7-sc6t_rev26-lef_cells_lvt", srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_L_1x_210923b.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_slvt", + name = "asap7-sc6t_rev26-lef_cells_slvt", srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_SL_1x_210923b.lef"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lef_sram", + name = "asap7-sc6t_rev26-lef_sram", srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_SRAM_1x_210923b.lef"], visibility = [":data_visibility"], ) @@ -222,7 +222,7 @@ filegroup( # Misc cells # FIXME: Where is the 1x techlef? #filegroup( -# name = "lef_tech", +# name = "asap7-sc6t_rev26-lef_tech", # srcs = ["asap7sc6t_26/techlef_misc/asap7_tech_1x_201209.lef"], # visibility = [":data_visibility"], #) @@ -232,33 +232,33 @@ filegroup( # Standard cells filegroup( - name = "lef_cells_4x_rvt", + name = "asap7-sc6t_rev26-lef_cells_4x_rvt", srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_R_4x_210923b.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_4x_lvt", + name = "asap7-sc6t_rev26-lef_cells_4x_lvt", srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_L_4x_210923b.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_4x_slvt", + name = "asap7-sc6t_rev26-lef_cells_4x_slvt", srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_SL_4x_210923b.lef"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lef_sram_4x", + name = "asap7-sc6t_rev26-lef_sram_4x", srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_SRAM_4x_210923b.lef"], visibility = [":data_visibility"], ) # Misc cell layouts for place and route filegroup( - name = "lef_tech_4x", + name = "asap7-sc6t_rev26-lef_tech_4x", srcs = ["asap7sc6t_26/techlef_misc/asap7_tech_4x_201209.lef"], visibility = [":data_visibility"], ) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev27.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27.bzl similarity index 83% rename from dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev27.bzl rename to dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27.bzl index 7b8ac4c5..f02f0076 100644 --- a/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev27.bzl +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27.bzl @@ -19,7 +19,7 @@ # Standard cells filegroup( - name = "gds_cells_rvt", + name = "asap7-sc7p5t_rev27-gds_cells_rvt", srcs = ["asap7sc7p5t_27/GDS/asap7sc7p5t_27_R_201211.gds"], visibility = [":data_visibility"], ) @@ -33,26 +33,26 @@ filegroup( # Standard cells filegroup( - name = "libgz_cells_rvt", + name = "asap7-sc7p5t_rev27-libgz_cells_rvt", srcs = glob(["asap7sc7p5t_27/LIB/CCS/*RVT*.lib.gz"]), visibility = [":data_visibility"], ) filegroup( - name = "libgz_cells_lvt", + name = "asap7-sc7p5t_rev27-libgz_cells_lvt", srcs = glob(["asap7sc7p5t_27/LIB/CCS/*LVT*.lib.gz"]), visibility = [":data_visibility"], ) filegroup( - name = "libgz_cells_slvt", + name = "asap7-sc7p5t_rev27-libgz_cells_slvt", srcs = glob(["asap7sc7p5t_27/LIB/CCS/*SLVT*.lib.gz"]), visibility = [":data_visibility"], ) # SRAM filegroup( - name = "libgz_sram", + name = "asap7-sc7p5t_rev27-libgz_sram", srcs = glob(["asap7sc7p5t_27/LIB/CCS/*SRAM*.lib.gz"]), visibility = [":data_visibility"], ) @@ -64,7 +64,7 @@ filegroup( # Standard cells filegroup( - name = "v_cells_rvt", + name = "asap7-sc7p5t_rev27-v_cells_rvt", srcs = [ "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_RVT_TT_210930.v", "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_RVT_TT_210930.v", @@ -76,7 +76,7 @@ filegroup( ) filegroup( - name = "v_cells_lvt", + name = "asap7-sc7p5t_rev27-v_cells_lvt", srcs = [ "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_LVT_TT_210930.v", "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_LVT_TT_210930.v", @@ -88,7 +88,7 @@ filegroup( ) filegroup( - name = "v_cells_slvt", + name = "asap7-sc7p5t_rev27-v_cells_slvt", srcs = [ "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_SLVT_TT_210930.v", "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_210930.v", @@ -101,7 +101,7 @@ filegroup( # SRAM filegroup( - name = "v_sram", + name = "asap7-sc7p5t_rev27-v_sram", srcs = [ "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_SRAM_TT_210930.v", "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_SRAM_TT_210930.v", @@ -117,26 +117,26 @@ filegroup( # Standard cells filegroup( - name = "lvs_cells_rvt", + name = "asap7-sc7p5t_rev27-lvs_cells_rvt", srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_R.cdl"], visibility = [":data_visibility"], ) filegroup( - name = "lvs_cells_lvt", + name = "asap7-sc7p5t_rev27-lvs_cells_lvt", srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_L.cdl"], visibility = [":data_visibility"], ) filegroup( - name = "lvs_cells_slvt", + name = "asap7-sc7p5t_rev27-lvs_cells_slvt", srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_SL.cdl"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lvs_sram", + name = "asap7-sc7p5t_rev27-lvs_sram", srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_SRAM.cdl"], visibility = [":data_visibility"], ) @@ -146,26 +146,26 @@ filegroup( # Standard cells filegroup( - name = "spice_cells_rvt", + name = "asap7-sc7p5t_rev27-spice_cells_rvt", srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_L_201024.sp"], visibility = [":data_visibility"], ) filegroup( - name = "spice_cells_lvt", + name = "asap7-sc7p5t_rev27-spice_cells_lvt", srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_R_201024.sp"], visibility = [":data_visibility"], ) filegroup( - name = "spice_cells_slvt", + name = "asap7-sc7p5t_rev27-spice_cells_slvt", srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_SL_201024.sp"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "spice_sram", + name = "asap7-sc7p5t_rev27-spice_sram", srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_SRAM_201024.sp"], visibility = [":data_visibility"], ) @@ -175,26 +175,26 @@ filegroup( # Standard cells filegroup( - name = "lef_cells_rvt", + name = "asap7-sc7p5t_rev27-lef_cells_rvt", srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_R_1x_201211.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_lvt", + name = "asap7-sc7p5t_rev27-lef_cells_lvt", srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_L_1x_201211.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_slvt", + name = "asap7-sc7p5t_rev27-lef_cells_slvt", srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_SL_1x_201211.lef"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lef_sram", + name = "asap7-sc7p5t_rev27-lef_sram", srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_SRAM_1x_201211.lef"], visibility = [":data_visibility"], ) @@ -207,33 +207,33 @@ filegroup( # Standard cells filegroup( - name = "lef_cells_4x_rvt", + name = "asap7-sc7p5t_rev27-lef_cells_4x_rvt", srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_4x_lvt", + name = "asap7-sc7p5t_rev27-lef_cells_4x_lvt", srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_4x_slvt", + name = "asap7-sc7p5t_rev27-lef_cells_4x_slvt", srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lef_sram_4x", + name = "asap7-sc7p5t_rev27-lef_sram_4x", srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef"], visibility = [":data_visibility"], ) # Misc cells filegroup( - name = "lef_tech_4x", + name = "asap7-sc7p5t_rev27-lef_tech_4x", srcs = ["asap7sc7p5t_27/techlef_misc/asap7_tech_4x_201209.lef"], visibility = [":data_visibility"], ) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev28.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28.bzl similarity index 82% rename from dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev28.bzl rename to dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28.bzl index c5af5a4b..8e8da88a 100644 --- a/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev28.bzl +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28.bzl @@ -12,6 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. + + """ ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. """ # Layouts for GDS generation @@ -19,26 +21,26 @@ # Standard cells filegroup( - name = "gds_cells_rvt", + name = "asap7-sc7p5t_rev28-rvt-cells-gds", srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_R_220121a.gds"], visibility = [":data_visibility"], ) filegroup( - name = "gds_cells_lvt", + name = "asap7-sc7p5t_rev28-lvt-cells-gds", srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_L_220121a.gds"], visibility = [":data_visibility"], ) filegroup( - name = "gds_cells_slvt", + name = "asap7-sc7p5t_rev28-slvt-cells-gds", srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_SL_220121a.gds"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "gds_sram", + name = "asap7-sc7p5t_rev28-srams-gds", srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_SRAM_220121a.gds"], visibility = [":data_visibility"], ) @@ -49,26 +51,26 @@ filegroup( # Standard cells filegroup( - name = "libgz_cells_rvt", + name = "asap7-sc7p5t_rev28-rvt-cells-libgz", srcs = glob(["asap7sc7p5t_28/LIB/CCS/*RVT*.lib.gz"]), visibility = [":data_visibility"], ) filegroup( - name = "libgz_cells_lvt", + name = "asap7-sc7p5t_rev28-lvt-cells-libgz", srcs = glob(["asap7sc7p5t_28/LIB/CCS/*LVT*.lib.gz"]), visibility = [":data_visibility"], ) filegroup( - name = "libgz_cells_slvt", + name = "asap7-sc7p5t_rev28-slvt-cells-libgz", srcs = glob(["asap7sc7p5t_28/LIB/CCS/*SLVT*.lib.gz"]), visibility = [":data_visibility"], ) # SRAM filegroup( - name = "libgz_sram", + name = "asap7-sc7p5t_rev28-srams-libgz", srcs = glob(["asap7sc7p5t_28/LIB/CCS/*SRAM*.lib.gz"]), visibility = [":data_visibility"], ) @@ -80,7 +82,7 @@ filegroup( # Standard cells filegroup( - name = "v_cells_rvt", + name = "asap7-sc7p5t_rev28-rvt-cells-v", srcs = [ # No CKINVDC "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_RVT_TT_201020.v", @@ -93,7 +95,7 @@ filegroup( ) filegroup( - name = "v_cells_lvt", + name = "asap7-sc7p5t_rev28-lvt-cells-v", srcs = [ # No CKINVDC "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_LVT_TT_201020.v", @@ -106,7 +108,7 @@ filegroup( ) filegroup( - name = "v_cells_slvt", + name = "asap7-sc7p5t_rev28-slvt-cells-v", srcs = [ # No CKINVDC "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_SLVT_TT_201020.v", @@ -120,7 +122,7 @@ filegroup( # SRAM filegroup( - name = "v_sram", + name = "asap7-sc7p5t_rev28-srams-v", srcs = [ # No CKINVDC "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_SRAM_TT_201020.v", @@ -137,26 +139,26 @@ filegroup( # Standard cells filegroup( - name = "lvs_cells_rvt", + name = "asap7-sc7p5t_rev28-rvt-cells-lvs", srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_R.cdl"], visibility = [":data_visibility"], ) filegroup( - name = "lvs_cells_lvt", + name = "asap7-sc7p5t_rev28-lvt-cells-lvs", srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_L.cdl"], visibility = [":data_visibility"], ) filegroup( - name = "lvs_cells_slvt", + name = "asap7-sc7p5t_rev28-slvt-cells-lvs", srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_SL.cdl"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lvs_sram", + name = "asap7-sc7p5t_rev28-srams-lvs", srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_SRAM.cdl"], visibility = [":data_visibility"], ) @@ -166,26 +168,26 @@ filegroup( # Standard cells filegroup( - name = "spice_cells_rvt", + name = "asap7-sc7p5t_rev28-rvt-cells-spice", srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_L.sp"], visibility = [":data_visibility"], ) filegroup( - name = "spice_cells_lvt", + name = "asap7-sc7p5t_rev28-lvt-cells-spice", srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_R.sp"], visibility = [":data_visibility"], ) filegroup( - name = "spice_cells_slvt", + name = "asap7-sc7p5t_rev28-slvt-cells-spice", srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_SL.sp"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "spice_sram", + name = "asap7-sc7p5t_rev28-srams-spice", srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_SRAM.sp"], visibility = [":data_visibility"], ) @@ -195,33 +197,33 @@ filegroup( # Standard cells filegroup( - name = "lef_cells_rvt", + name = "asap7-sc7p5t_rev28-rvt-cells-lef", srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_R_1x_220121a.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_lvt", + name = "asap7-sc7p5t_rev28-lvt-cells-lef", srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_L_1x_220121a.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_slvt", + name = "asap7-sc7p5t_rev28-slvt-cells-lef", srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_SL_1x_220121a.lef"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lef_sram", + name = "asap7-sc7p5t_rev28-srams-lef", srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_SRAM_1x_220121a.lef"], visibility = [":data_visibility"], ) # Misc cells filegroup( - name = "lef_tech", + name = "asap7-sc7p5t_rev28-tech-lef", srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], visibility = [":data_visibility"], ) @@ -231,33 +233,33 @@ filegroup( # Standard cells filegroup( - name = "lef_cells_4x_rvt", + name = "asap7-sc7p5t_rev28_4x-rvt-cells-lef", srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_R_4x_201211.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_4x_lvt", + name = "asap7-sc7p5t_rev28_4x-lvt-cells-lef", srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_L_4x_201211.lef"], visibility = [":data_visibility"], ) filegroup( - name = "lef_cells_4x_slvt", + name = "asap7-sc7p5t_rev28_4x-slvt-cells-lef", srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_SL_4x_201211.lef"], visibility = [":data_visibility"], ) # SRAM filegroup( - name = "lef_sram_4x", + name = "asap7-sc7p5t_rev28_4x-srams-lef", srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_SRAM_4x_201211.lef"], visibility = [":data_visibility"], ) # Misc cells filegroup( - name = "lef_tech_4x", + name = "asap7-sc7p5t_rev28_4x-lef_tech", srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_4x_201209.lef"], visibility = [":data_visibility"], ) diff --git a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel index 79a9a4ac..f6f94dc5 100644 --- a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel @@ -39,26 +39,48 @@ the 7.5 track library using RVT transistors and slow corner. load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cell_library") +#load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7sc6t_rev26.bzl", "asap7_cell_library") +#load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7sc7p5t_rev27.bzl", "asap7_cell_library") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7-sc7p5t_rev28.bzl", "*") -# FIXME - Use the asap7scXXXX.bzl files. +#asap7_cell_library( +# name = "asap7-sc6t_rev26_lvt-tt", +# srcs = [ +# ":asap7-sc6t_rev26_lvt-cells-libgz", +# ":asap7-sc6t_rev26_lvt-sram-libgz", +# ], +# cell_lef = ":asap7-sc6t_rev26_lvt-cells-lvt-libgz", +# cell_type = "LVT", +# platform_gds = "", +# default_corner_delay_model = "ccs", +# default_corner_swing = "SS", +# openroad_configuration = ":open_road_asap7_1x", +# tech_lef = "", +# visibility = [ +# "//visibility:public", +# ] +#) asap7_cell_library( - name = "asap7_rvt_tt", - srcs = glob(["asap7sc7p5t_28/LIB/CCS/*.lib.gz"]), - cell_lef = "asap7sc7p5t_28/LEF/asap7sc7p5t_28_R_1x_220121a.lef", + name = "asap7-sc7p5t_rev28_rvt-ss", + srcs = [ + ":asap7-sc7p5t_rev28_rvt-cells-libgz", +# ":asap7-sc7p5t_rev28-srams-libgz", + ], + cell_lef = ":asap7-sc7p5t_rev28_rvt-cells-lef", cell_type = "RVT", - platform_gds = "asap7sc7p5t_28/GDS/asap7sc7p5t_28_R_220121a.gds", + platform_gds = ":asap7-sc7p5t_rev28_rvt-cells-gds", default_corner_delay_model = "ccs", default_corner_swing = "SS", openroad_configuration = ":open_road_asap7_1x", - tech_lef = "asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef", + tech_lef = ":asap7-sc7p5t_rev28-tech-lef", visibility = [ "//visibility:public", ] ) open_road_pdk_configuration( - name = "open_road_asap7_1x", + name = "open_road-asap7-sc7p5t_rev28_rvt-ss", cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [