From 5004e00a4ff5faa0eb0c322ca7ae8503bd4606ed Mon Sep 17 00:00:00 2001 From: Aurumaker72 Date: Wed, 27 Nov 2024 17:13:50 +0100 Subject: [PATCH] Core/ST: Fix missing SI interrupt in queue when savestating on pure interpreter Fixes regression from f9d58f6 --- core/memory/savestates.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/core/memory/savestates.cpp b/core/memory/savestates.cpp index ed2f5767..a472d719 100644 --- a/core/memory/savestates.cpp +++ b/core/memory/savestates.cpp @@ -199,8 +199,6 @@ namespace Savestates memset(g_flashram_buf, 0, sizeof(g_flashram_buf)); memset(g_event_queue_buf, 0, sizeof(g_event_queue_buf)); - save_flashram_infos(g_flashram_buf); - const int event_queue_len = save_eventqueue_infos(g_event_queue_buf); uint32_t movie_active = VCR::get_task() != e_task::idle; if (FIX_NEW_ST) @@ -229,6 +227,10 @@ namespace Savestates //hack end } + // NOTE: This saving needs to be done **after** the fixing block, as it is now. See previous regression in f9d58f639c798cbc26bbb808b1c3dbd834ffe2d9. + save_flashram_infos(g_flashram_buf); + const int event_queue_len = save_eventqueue_infos(g_event_queue_buf); + vecwrite(b, rom_md5, 32); vecwrite(b, &rdram_register, sizeof(RDRAM_register)); vecwrite(b, &MI_register, sizeof(mips_register));